Gigatron Hackers

That's a neat way to do that.

Another idea comes to mind. What if there were a way to drive the ALU (and possibly the CU) at twice the main frequency? Then that could allow up to 4 native instructions (assuming multiple ALUs). That could allow hardware blitting and 16-bit ops (due to having 2 RAM cycles per ROM cycle). That woul...

I still haven't started my Verilog CPU project. I'd like to make something that can run vCPU code, but with a different architecture. I'm looking for comments on various aspects or any considerations. Separation of video/sound/keyboard using DMA -- This will use the redirection table for the video. ...

The image above shows this bug with all the spikes in the image around all horizontal edges. I am not sure if the double-buffering is the cause since the original design was made to work with HDMI.

To go beyond a little past 12 Mhz, that is where you start to rethink other things. Redesigning the ALU to use a carry-skip adder configuration would likely help because that would allow both carry possibilities to be calculated at the same time with a minor switching delay rather than calculating t...

Going that far, if one wants to merge the repeater board and the I/O board, one might as well boost the ALU speed too. The adders are right below the repeater, and the high adder is the one I'd replace with a reduced latency adder board. You can use 2 adders and a multiplexer in place of the upper a...

The above is why in my FPGA design, I'd be using DMA with hardware-only syncs and moving all I/O to hardware. So everything that needs the syncs would have direct physical access to them. That would prevent hardware races. Software races would be more difficult to avoid. In this configuration, you'd...

My own idea is to have concurrent DMA of some sort and clock the video side at 6.25 and/or 12.5, and generate the correct syncs. To prevent I/O races, it would probably be easier to put sound and keyboard support in hardware too. Otherwise, one would need to do parallel syncs in software, add haltin...

While planning for doing an FPGA design, I've considered the feasibility of doing hardware interrupts. That would make it easier to separate out the video since the syncs could trigger interrupts, and it could make native coding a little easier. Now, the first thing to do is reflect on all the opera...

1. Use a faster clock rate, lower latency chips, more compact board. 2. Separating the video. This change could allow the core unit to be clocked faster than the video. I may use some type of DMA and make the controller indirection table aware in my own variation. That should keep compatibility. The...