Search found 48 matches
- 26 Jan 2020, 05:27
- Forum: Hardware and software hacking
- Topic: Modified Gigatron Design Ideas
- Replies: 57
- Views: 60882
Re: Opcode mods
On the ROM control unit idea, if you can't get faster than 45ns then the theoretical maximum would be 22 Mhz, assuming you use a pipeline arrangement. One could transfer that to registers and do on a future cycle if necessary. One way to speed things up would be to shadow it, so with 10ns SRAM, you ...
- 22 Jan 2020, 02:14
- Forum: Hardware and software hacking
- Topic: Modified Gigatron Design Ideas
- Replies: 57
- Views: 60882
Re: Opcode mods
Thanks, now I understand. And yes, I didn't think of that issue. But an external device reset pin could still be of use. In the case of a video card, it could instead signal to not display data until the next frame. So if it has memory, it can then load the memory from the start without display unti...
- 18 Jan 2020, 18:24
- Forum: Hardware and software hacking
- Topic: Modified Gigatron Design Ideas
- Replies: 57
- Views: 60882
Re: Modified Gigatron Design Ideas
I've been thinking about Ben Eater's "video card" design. I was pondering how to modify it to where the syncs could be modified by software. I think I've discovered a way to do that. Instead of using hardwired logic gates, a register and a digital comparator would be better. So the pixel c...
- 18 Jan 2020, 18:22
- Forum: Hardware and software hacking
- Topic: Modified Gigatron Design Ideas
- Replies: 57
- Views: 60882
Re: Opcode mods
A clarification. I've never said that the CPU has any hidden states. My idea to piggyback onto a NOP instruction is only for external devices. For instance, if an external video controller is used and there is the chance of losing the syncs or not knowing where the raster is, one of the spare NOPs c...
- 20 Dec 2019, 07:22
- Forum: Escape Meta Alt Control Shift
- Topic: C74-6502
- Replies: 7
- Views: 9339
Re: C74-6502
No, but I think Dieter does. He has read some of my posts.marcelk wrote: ↑14 Dec 2019, 16:31 I doubt Drass is reading this forum. But you can propose your enhancement in the design thread on the 6502 forum: http://forum.6502.org/viewtopic.php?f=4&t=3493
- 19 Dec 2019, 08:41
- Forum: Hardware and software hacking
- Topic: Modified Gigatron Design Ideas
- Replies: 57
- Views: 60882
Re: Opcode mods
Another mod that came to mind, though likely not attractive to use, would be replacing most of the instruction decoder with a ROM. The instruction register can drive the address lines and the data lines drive the control lines. So this replaces the logic with an instruction map. There would be no sp...
- 15 Dec 2019, 17:48
- Forum: Escape Meta Alt Control Shift
- Topic: C74-6502
- Replies: 7
- Views: 9339
Re: C74-6502
Yeah, but the FPGA in the Eclaire goes about 50 Mhz. The Eclaire implements the majority of the Atari 800, etc., in FPGA. So the "Sally" 6502, Antic, GTIA, PIA, and 2 Pokeys are all on a single chip. The original Ataris only use 1 Pokey for ports, keyboard, and sound. However, arcade games...
- 14 Dec 2019, 21:04
- Forum: Escape Meta Alt Control Shift
- Topic: C74-6502
- Replies: 7
- Views: 9339
Re: C74-6502
Yeah, thanks, that would be a good idea. Adding the /halt line to the design would increase compatibility with vintage systems. The Ataris that used the 6502 mostly used the "Sally" variant with the halt pin, though some of the older Ataris didn't use it. So they got MOS to add the halt li...
- 13 Dec 2019, 21:30
- Forum: Escape Meta Alt Control Shift
- Topic: C74-6502
- Replies: 7
- Views: 9339
Re: C74-6502
Yes, that is neat, and I bet it could go even faster when implemented in FPGA (and one implemented that way will do about 50 Mhz). But I see one shortcoming that should be easy to address. It seems to lack the "Sally" compatibility, so it won't work with an Atari computer without adding 4 ...
- 05 Dec 2019, 15:50
- Forum: Hardware and software hacking
- Topic: Modified Gigatron Design Ideas
- Replies: 57
- Views: 60882
Thinking of creating a custom CPU
I am not committed yet, but I've been considering a custom CPU. I am only in the crude planning stages about the architecture I'd want. I'd likely need to learn how to do FPGA, especially if I were to do 32 or more bits. So I'd need to get accustomed to using FPGA design software and Verilog/HDL. No...