Gigatron Hackers

If you want to just emulate the Von Neumann vCPU 16bit instruction set, that's pretty trivial on any decent modern architecture. If you want 100% .gt1 compatibility then you have to emulate all the Sys calls, zero page registers, audio registers, VBlank registers, scanline VTable, etc, etc. No so t...

I wanted to do the 75-100 Mhz Gigatron, and while I think that's possible if I redesign the architecture and go for a 4-stage pipeline, I don't know if I can pull it off with the way memory prices have gotten. While that's against Marcel's original philosophy, I wanted to do the CU and the ALU in SR...

My idea on that would be to put the 2 Gigatrons on opposing clocks and make the RAM only available to the active one. So concurrent DMA where 1 works half the time and the other works half the time. So they each get to use the memory during their turn. So round-robin arbitration. I can think of diff...

In an old thread, Marcel gave a way to join 2 Gigatrons. I recently thought of a different way to do it. Someone could take 2 Gigatrons, use a 2-phase clock, and connect them using the memory. So let one do all the I/O and the other just run vCPU, and a somewhat simpler one due to not needing to car...

I recently thought of a different idea. Maybe if someone were to take 2 Gigatrons, use a 2-phase clock, and connect them at the memory. So let one do all the I/O and the other just run vCPU, and a somewhat simpler one due to not needing to care about time slices. The I/O one could handle video, soun...

It's an assembly/soldering optimisation, just solder the pins together and you don't have to worry about extra wires, routing, etc. The RAM could care less which bytes your address lines access, as long as the address mapping is always consistent and always matches the 64k address space in a 1:1 fa...

You can get a 128KB one and wire the extra address pins together. https://www.digikey.com/en/products/detail/alliance-memory-inc/AS6C1008-55PCN/4234576 Or you can bite the bullet and build a 128KB expansion which also gives you SPI port usable with a SD card. (see https://forum.gigatron.io/viewtopi...

Would an instruction where you multiply something in memory and then jump to that address (all in a single cycle) be helpful in designing a more efficient vCPU? So you could space out the landings of the jump table wider. And if I were to add that, what would be more helpful? Causing the extra bits ...

Just an update. I still need to find suitable ROM and RAM. On ROM, it seems to be most of what I'd consider is discontinued, and the rest is on backorder. Any suggestions? Does anyone know of any ALU ops I should add? While 512K memory for an ALU would be enough to provide the functionality of the G...

That's why I said to tap the ROM and the accumulator since it's a Harvard arch. Tapping both ROM and RAM would give the most additional instructions. When registers other than Ac (since I propose tapping that too) are used, the instructions could be replaced on the fly on the Gigatron side. So if yo...