Gigatron Hackers

Hi, I've made a few calculations and I found the Gigatron is already overclocked! Let's check it again: In the Gigatron we got two blocks running in parallel: Fetch Unit: PC plus EPROM pus IR registers. The minimun clock period is going to be: Tmin = delay_PC + delay_EPROM + setup_time_IR = 15ns + 7...

Hi, I'm very pleased to find this nice and clever computer design. And well documented too. In this regard I found in the schematic you're using germanium diodes for logic (at least for the AND gate, in decoding ROMs the diode model is not specified). This looks odd, and in fact, the videos and phot...