Assembling Gigatron the hard way

Questions and discussions about assembling a Gigatron kit: from box to baboon. Build photos also!
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pythag
Posts: 21
Joined: 21 Apr 2019, 20:29

Assembling Gigatron the hard way

Post by pythag » 21 Apr 2019, 20:56

Hi Folks,

Just thought I'd say 'hi' and introduce myself...

I bought a Gigatron a few months ago to work on with my son as a bit of a project to do together, however to make it more interesting than just a soldering project (he's done enough of those already) we're building it on a breadboard!. The purchase actually came about as he'd been making some simple circuits on breadboards and asked 'is it possible to make a computer on a breadboard?'... I Googled, imaging I'd fine an interesting Z80 based project that we could build when I found the Gigatron and figured that was far more exciting.

Current state of play:

It's taken him about 6 weeks of doing the odd half an hour every so often and it's finally 'finished' (i.e. he believes all connections are made). I then checked and didn't find any obvious mistakes - although all I really did was check power and ground was correct on all ICs and that if there were any ICs with pins not connected to anything that matched the schematic.

I clearly didn't do my checking as thoroughly as I should as there was a mistake - Vcc of U8 was connected to ground instead of Vcc... Thankfully I'd powered it up on a bench supply with the limit set at 100mA so although it did hit the current limit all seems fine (U8 still seems to be functioning as expected).

After fixing that issue we got a bit further, but still nothing on screen. Probing the ROM address bus I can see that it halts when the memory address test fails (I see it sit in the loop at address 0x0A):

Code: Select all

# Give a first sign of life that can be checked with a voltmeter
ld(0b0000);                     C('LEDs |OOOO|')
ld(syncBits^hSync, OUT)         # Prepare XOUT update, hSync goes down, RGB to black
ld(syncBits, OUT)               # hSync goes up, updating XOUT

# Simple RAM test and size check by writing to [1<<n] and see if [0] changes.
ld(1);                          C('RAM test and count')
label('.countMem0')
st([memSize], Y)
ld(255)
xora([Y,0])
st([Y,0])                       # Test if we can change and read back ok
st([0])                         # Preserve (inverted) memory value in [0]
xora([Y,0])
bne(pc()) # Just hang here on apparent RAM failure
...probing that was as far as we got today

For tomorrows tinkering I've written a small Arduino utility... It takes control of the reset and clock lines and allows me to single step the Gigatron, whilst the remaining pins act as a crude logic analyser. After the mini-me had gone to bed I tested it and confirmed it captures the looping behavior I'd already observed by monitoring the ROM address lines.

So possible faults:
(1) Something wrong in the condition decoder logic
(2) Something wrong in the RAM interface
(3) Something wrong in the addressing mode decoder

My money is on #3 given the messyness of the assembly.... (I did suggest he lay it out in a grid on the breadboard, but of course he knows best...)

Wish us luck!

M.

pythag
Posts: 21
Joined: 21 Apr 2019, 20:29

Re: Assembling Gigatron the hard way

Post by pythag » 21 Apr 2019, 21:09

So having spend most of this evening making my own Arduino based tester I discover this in the repository:

https://github.com/xopr/gigatron-tester ... tester.ino

Still, this will be very useful as it's far more featured than mine....

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marcelk
Posts: 252
Joined: 13 May 2018, 08:26

Re: Assembling Gigatron the hard way

Post by marcelk » 21 Apr 2019, 23:57

Wow, that's cool. It's definitely possible of course. PLEASE share photos. If you're hanging in the mem test's infinite loop, it's pretty close to working already!

My original diode decoding looks like this, and believe it or not, I never had any issues with this part of the prototype.

IMG_5173.jpeg
IMG_5173.jpeg (303.84 KiB) Viewed 262 times

As a general advice, beware of voltage differences across the boards for Vcc and GND. In the end I ran a lot of random patch wires across the system to make it even. (Although CMOS is probably quite forgiving compared to bipolar)

I now see that I used a (74LS)155 for the instruction decoder, what is now a 74x138. Also I should upgrade the board to the current software...

For those who wonder about the colors in the Gigatron block diagram: they match the Velleman wire colors in this prototype. For example, the two yellow wires are EL and EH running to the MAU. The MAU is a yellow block in the diagram. Grey is control unit. Orange is ALU. Now you know...

P.S. At VCF PNW somebody told me he had built one on a breadboard with his son. That wasn't you I suppose?

pythag
Posts: 21
Joined: 21 Apr 2019, 20:29

Re: Assembling Gigatron the hard way

Post by pythag » 22 Apr 2019, 12:41

So after testing this morning I've ruled out a few causes:

* Both the instruction decoder and address mode decoder diode logic is working fine (much to my surprise!)
* The issue seems to revolve around the loading of the AC register... My AC7 line is first asserted at instruction 0x07 ("0007 ca00 st [y,$00]") - this matches the simulation, however when my Gigatron runs instruction 0x08 ("0008 c200 st [$00]") my AC7 line gets cleared, whereas it stays asserted on the simulation.
* I've verified that on instruction 0x08 the LD line is high, so new contents shouldn't have been loaded into the AC register (I've verified the LD line for all the first 10 instructions against the simulation - perfect match).

I might have to get the scope out again and see what the signal at pin 1 of U27 actually looks like - maybe it's too slow to rise. In my Arduino based testing I left the pair of not gates in to provide the delayed CLK2 - maybe I should also generate this on the Arduino and put a larger delay in. I don't have a digital scope (mine is ex-MOD and is dated 1972!!!), so it's hard to measure rise times on single events.

Photos coming soon.... If I post them now everyone will just say I've no hope of getting it working ;-) It really does look like it was built by an 8-year old! It wasn't you met at VCF - wrong part of the world for me. I did mention I planned to build it on a breadboard when I purchased it though...

M.

pythag
Posts: 21
Joined: 21 Apr 2019, 20:29

Re: Assembling Gigatron the hard way

Post by pythag » 22 Apr 2019, 19:30

So, latest Observations:

(I'm mostly writing this post to force me to explain what I'm observing properly so I spot what I'm obviously missing - I may not even click 'submit!'):

I'm now using the Arduino to generate a delayed CLK2.

Below is the combined output of:
1st line - disassembly from ROMv3.asm
2nd line - debug I've dumped out from the simulator after the CpuState has been updated
3rd line - the data captured by the Arduino after a clock pulse has been issued

(I know it would have helped readability if I'd kept the same format for both simulation and capture!!!)

Code: Select all

              0000 0000  ld   $00         ;LEDs |OOOO|
1:  LD  A:0001 ins:0 lines: 0011-0 mod:0 lines: 1110 bus:0 W:0 J:0 AC:00, AC7: 0, LD:0
1   A5-A0:0,0,0,0,0,1 (01)  R5(5-2):0,0,1,1   ST,W,R4(2),!LD:1,0,0,0   AC7:0

              0001 1880  ld   $80,out
2:  LD  A:0002 ins:0 lines: 0011-0 mod:6 lines: 1101 bus:0 W:0 J:0 AC:00, AC7: 0, LD:1
2   A5-A0:0,0,0,0,1,0 (02)  R5(5-2):0,0,1,1   ST,W,R4(2),!LD:1,0,1,1   AC7:0

              0002 18c0  ld   $c0,out
3:  LD  A:0003 ins:0 lines: 0011-0 mod:6 lines: 1101 bus:0 W:0 J:0 AC:00, AC7: 0, LD:1
3   A5-A0:0,0,0,0,1,1 (03)  R5(5-2):0,0,1,1   ST,W,R4(2),!LD:1,0,1,1   AC7:0

              0003 0001  ld   $01         ;RAM test and count
4:  LD  A:0004 ins:0 lines: 0011-0 mod:0 lines: 1110 bus:0 W:0 J:0 AC:00, AC7: 0, LD:0
4   A5-A0:0,0,0,1,0,0 (04)  R5(5-2):0,0,1,1   ST,W,R4(2),!LD:1,0,0,0   AC7:0

.countMem0:   0004 d601  st   [$01],y
5:  ST  A:0005 ins:6 lines: 1111-1 mod:5 lines: 1111 bus:2 W:1 J:0 AC:01, AC7: 0, LD:1
5   A5-A0:0,0,0,1,0,1 (05)  R5(5-2):1,1,1,1   ST,W,R4(2),!LD:0,1,1,1   AC7:0

              0005 00ff  ld   $ff
6:  LD  A:0006 ins:0 lines: 0011-0 mod:0 lines: 1110 bus:0 W:0 J:0 AC:01, AC7: 0, LD:0
6   A5-A0:0,0,0,1,1,0 (06)  R5(5-2):0,0,1,1   ST,W,R4(2),!LD:1,0,0,0   AC7:1

              0006 6900  xora [y,$00]
7:  XOR A:0007 ins:3 lines: 1001-0 mod:2 lines: 0110 bus:1 W:0 J:0 AC:ff, AC7: 1, LD:0
7   A5-A0:0,0,0,1,1,1 (07)  R5(5-2):1,0,0,1   ST,W,R4(2),!LD:1,0,0,0   AC7:0

              0007 ca00  st   [y,$00]
8:  ST  A:0008 ins:6 lines: 1111-1 mod:2 lines: 0110 bus:2 W:1 J:0 AC:4f, AC7: 0, LD:1
8   A5-A0:0,0,1,0,0,0 (08)  R5(5-2):1,1,1,1   ST,W,R4(2),!LD:0,1,0,1   AC7:0

              0008 c200  st   [$00]
9:  ST  A:0009 ins:6 lines: 1111-1 mod:0 lines: 1110 bus:2 W:1 J:0 AC:4f, AC7: 0, LD:1
9   A5-A0:0,0,1,0,0,1 (09)  R5(5-2):1,1,1,1   ST,W,R4(2),!LD:0,1,0,1   AC7:0

              0009 6900  xora [y,$00]
10: XOR A:000a ins:3 lines: 1001-0 mod:2 lines: 0110 bus:1 W:0 J:0 AC:4f, AC7: 0, LD:0
10  A5-A0:0,0,1,0,1,0 (0A)  R5(5-2):1,0,0,1   ST,W,R4(2),!LD:1,0,0,0   AC7:1

              000a ec0a  bne  $000a
11: BCC A:000b ins:7 lines: 1010-0 mod:3 lines: 0010 bus:0 W:0 J:1 AC:00, AC7: 0, LD:0
11  A5-A0:0,0,1,0,1,1 (0B)  R5(5-2):1,0,1,0   ST,W,R4(2),!LD:1,0,1,1   AC7:1
All is well up until it has just run the instruction '0005 00ff ld $ff'...

After that point my AC7 goes high, where as the simulation result shows low... This doesn't happen until the following clock cycle in the simulation.

To make it even stranger I've looked back at previous captures I did with the Arduino (when I was still using the 74HC04 to generate the delayed CLK2) and I don't see that shift - so this seems to be an extra problem I've created by adding more delay to CLK2.

pythag
Posts: 21
Joined: 21 Apr 2019, 20:29

Re: Assembling Gigatron the hard way

Post by pythag » 22 Apr 2019, 20:37

Okay, I must be tired here.... Just looking over the previous trace and logically (in my head at least) the captured data is correct and the simulation wrong:

Code: Select all

              0005 00ff  ld   $ff
Sim 6:  LD  A:0006 ins:0 lines: 0011-0 mod:0 lines: 1110 bus:0 W:0 J:0 AC:01, AC7: 0, LD:0
Cap 6:        A:0006 R5(5-2):0,0,1,1   ST,W,R4(2),!LD:1,0,0,0   AC7:1
...so it has just run the "ld $ff" instruction - this, as far as I understand, places 0xFF into the AC register.... How is the contents of the 'AC' register set to 0x01 after that instruction?.... The captured result of AC7 being high matches having placed 0xFF into the AC register....

I think I must have got myself thoroughly confused about what I'm printing out where... It all looks correct though - the PC has been updated (+1), whilst the instruction register contains the contents of the previous ROM[PC] as expected.

I'll sleep on it and try with a fresh mind tomorrow. I can't help feeling I'm missing something obvious here.... (perhaps I'm just living in denial that the issue is actually the CO signal into U12 (condition decoder) - that's a rabbit hole I really don't want to go down...).

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marcelk
Posts: 252
Joined: 13 May 2018, 08:26

Re: Assembling Gigatron the hard way

Post by marcelk » 23 Apr 2019, 00:25

The simulation is weird. ld $ff definitely makes AC7 high.

I've seen one board that didn't come through the mem test, and it turned out to be an ungrounded condition decoder IC (cold solder joint).

pythag
Posts: 21
Joined: 21 Apr 2019, 20:29

Re: Assembling Gigatron the hard way

Post by pythag » 28 Apr 2019, 00:24

Hi Folks,

Is there a written guide / notes to Gigatron assembly language anywhere (perhaps as comments in the compiler source somewhere)?

I'm really trying to wrap my head around what the first 20 instructions or so do...

Code: Select all

              0000 0000  ld   $00         ;LEDs |OOOO|
              0001 1880  ld   $80,out
              0002 18c0  ld   $c0,out
              0003 0001  ld   $01         ;RAM test and count
.countMem0:   0004 d601  st   [$01],y
              0005 00ff  ld   $ff
              0006 6900  xora [y,$00]
              0007 ca00  st   [y,$00]
              0008 c200  st   [$00]
              0009 6900  xora [y,$00]
              000a ec0a  bne  $000a
              000b 00ff  ld   $ff
              000c 6900  xora [y,$00]
              000d ca00  st   [y,$00]
              000e 6100  xora [$00]
              000f f013  beq  .countMem1
Instructions 0 to 3 are obvious... then I get slightly confused.

I'm *extra* confused because I put the simulator code onto the same Arduino I'm using as a logic analyser (with a few adjustments) and it exhibits exactly the same behavior as my breadboard one does....

Logically this obviously means I've made some mistake with the simulator code (as it clearly runs correctly on my PC).

Here is the data from my run (up to the point of looping):

The first block of any clock cycle (so the lines that begin ROM, IR and Y) are the lines sampled from the breadboard. The lines beginning PC and D are the output from the Arduino based simulator. For now ignore the recorded values in 'DATA', 'Y', and 'AC' on the breadboard as I've not connected those to the analyser yet (I ram out of wire). The BUS, ROM ADR and IR lines are connected though, as are the individual control lines (e.g. YL, XL etc...).

Code: Select all

Clock cycle:1  ROM Lookup: IR:0 D:0

ROM ADR:0001 BUS:00 (000000000) Data:00 (000000000)
IR:00 [ins:0-LD  00011 mod:0-1110 bus-0000-ROM W:0 J:0 LD:0 ]
Y:00 (000000000) AC:00 (000000000) YL:1 XL:1 EH:1 EL:1 OL:1 LD:0 PL:1 PH:1

PC:1 IR:00 [ins:0-LD  00011 mod:0-1110 bus-0000-ROM W:0 J:0 LD:0 ]
D:00 AC:00 (000000000) X:00 Y:00
---------------                                                                 
Clock cycle:2  ROM Lookup: IR:18 D:80                                           
                                                                                
ROM ADR:0002 BUS:80 (010000000) Data:01 (000000001)                             
IR:18 [ins:0-LD  00011 mod:6-1101 bus-0000-ROM W:0 J:0 LD:1 ]                   
Y:00 (000000000) AC:00 (000000000) YL:1 XL:1 EH:1 EL:1 OL:0 LD:1 PL:1 PH:1      
                                                                                
PC:2 IR:18 [ins:0-LD  00011 mod:6-1101 bus-0000-ROM W:0 J:0 LD:1 ]              
D:80 AC:00 (000000000) X:00 Y:00                                                
---------------                                                                 
Clock cycle:3  ROM Lookup: IR:18 D:C0                                           
                                                                                
ROM ADR:0003 BUS:C0 (011000000) Data:01 (000000001)                             
IR:18 [ins:0-LD  00011 mod:6-1101 bus-0000-ROM W:0 J:0 LD:1 ]                   
Y:00 (000000000) AC:00 (000000000) YL:1 XL:1 EH:1 EL:1 OL:0 LD:1 PL:1 PH:1      
                                                                                
PC:3 IR:18 [ins:0-LD  00011 mod:6-1101 bus-0000-ROM W:0 J:0 LD:1 ]              
D:C0 AC:00 (000000000) X:00 Y:00                                                
---------------                                                                 
Clock cycle:4  ROM Lookup: IR:0 D:1                                             
                                                                                
ROM ADR:0004 BUS:01 (000000001) Data:00 (000000000)                             
IR:00 [ins:0-LD  00011 mod:0-1110 bus-0000-ROM W:0 J:0 LD:0 ]                   
Y:00 (000000000) AC:00 (000000000) YL:1 XL:1 EH:1 EL:1 OL:1 LD:0 PL:1 PH:1      
                                                                                
PC:4 IR:00 [ins:0-LD  00011 mod:0-1110 bus-0000-ROM W:0 J:0 LD:0 ]              
D:01 AC:00 (000000000) X:00 Y:00                                                
---------------                                                                 
Clock cycle:5  ROM Lookup: IR:D6 D:1                                            
                                                                                
ROM ADR:0005 BUS:81 (010000001) Data:03 (000000011)                             
IR:D6 [ins:6-ST  11111 mod:5-1111 bus-0010-AC  W:1 J:0 LD:1 ]                   
Y:00 (000000000) AC:00 (000000000) YL:1 XL:1 EH:1 EL:1 OL:1 LD:1 PL:1 PH:1      
                                                                                
PC:5 IR:D6 [ins:6-ST  11111 mod:5-1111 bus-0010-AC  W:1 J:0 LD:1 ]              
D:01 AC:01 (000000001) X:00 Y:00                                                
---------------                                                                 
Clock cycle:6  ROM Lookup: IR:0 D:FF                                            
                                                                                
ROM ADR:0006 BUS:FF (011111111) Data:00 (000000000)                             
IR:00 [ins:0-LD  00011 mod:0-1110 bus-0000-ROM W:0 J:0 LD:0 ]                   
Y:00 (000000000) AC:00 (000000000) YL:1 XL:1 EH:1 EL:1 OL:1 LD:0 PL:1 PH:1      
                                                                                
Writing 1 to address 1                                                          
PC:6 IR:00 [ins:0-LD  00011 mod:0-1110 bus-0000-ROM W:0 J:0 LD:0 ]              
D:FF AC:01 (000000001) X:00 Y:01                                                
---------------                                                                 
Clock cycle:7  ROM Lookup: IR:69 D:0                                            
                                                                                
ROM ADR:0007 BUS:FF (011111111) Data:00 (000000000)                             
IR:69 [ins:3-XOR 01001 mod:2-0110 bus-0001-RAM W:0 J:0 LD:0 ]                   
Y:00 (000000000) AC:00 (000000000) YL:1 XL:1 EH:0 EL:1 OL:1 LD:0 PL:1 PH:1      
                                                                                
PC:7 IR:69 [ins:3-XOR 01001 mod:2-0110 bus-0001-RAM W:0 J:0 LD:0 ]              
D:00 AC:FF (011111111) X:00 Y:01                                                
---------------                                                                 
Clock cycle:8  ROM Lookup: IR:CA D:0                                            
                                                                                
ROM ADR:0008 BUS:80 (010000000) Data:02 (000000010)                             
IR:CA [ins:6-ST  11111 mod:2-0110 bus-0010-AC  W:1 J:0 LD:1 ]                   
Y:00 (000000000) AC:00 (000000000) YL:1 XL:1 EH:0 EL:1 OL:1 LD:1 PL:1 PH:1      
                                                                                
Read uninit from 256                                                            
PC:8 IR:CA [ins:6-ST  11111 mod:2-0110 bus-0010-AC  W:1 J:0 LD:1 ]              
D:00 AC:00 (000000000) X:00 Y:01                                                
---------------                                                                 
Clock cycle:9  ROM Lookup: IR:C2 D:0                                            
                                                                                
ROM ADR:0009 BUS:80 (010000000) Data:02 (000000010)                             
IR:C2 [ins:6-ST  11111 mod:0-1110 bus-0010-AC  W:1 J:0 LD:1 ]                   
Y:00 (000000000) AC:00 (000000000) YL:1 XL:1 EH:1 EL:1 OL:1 LD:1 PL:1 PH:1      
                                                                                
Writing 0 to address 256                                                        
PC:9 IR:C2 [ins:6-ST  11111 mod:0-1110 bus-0010-AC  W:1 J:0 LD:1 ]              
D:00 AC:00 (000000000) X:00 Y:01                                                
---------------                                                                 
Clock cycle:10  ROM Lookup: IR:69 D:0                                           
                                                                                
ROM ADR:000A BUS:80 (010000000) Data:00 (000000000)                             
IR:69 [ins:3-XOR 01001 mod:2-0110 bus-0001-RAM W:0 J:0 LD:0 ]                   
Y:00 (000000000) AC:00 (000000000) YL:1 XL:1 EH:0 EL:1 OL:1 LD:0 PL:1 PH:1      
                                                                                
Writing 0 to address 0                                                          
PC:10 IR:69 [ins:3-XOR 01001 mod:2-0110 bus-0001-RAM W:0 J:0 LD:0 ]             
D:00 AC:00 (000000000) X:00 Y:01                                                
---------------                                                                 
Clock cycle:11  ROM Lookup: IR:EC D:A                                           
                                                                                
ROM ADR:000B BUS:0A (000001010) Data:01 (000000001)                             
IR:EC [ins:7-BCC 01010 mod:3-1111 bus-0000-ROM W:0 J:1-cond LD:1 ]              
Y:00 (000000000) AC:00 (000000000) YL:1 XL:1 EH:1 EL:1 OL:1 LD:1 PL:0 PH:1      
                                                                                
Read uninit from 256                                                            
PC:11 IR:EC [ins:7-BCC 01010 mod:3-1111 bus-0000-ROM W:0 J:1-cond LD:1 ]        
D:0A AC:FF (011111111) X:00 Y:01                                                
---------------                                                                 
Clock cycle:12  ROM Lookup: IR:69 D:0                                           
                                                                                
ROM ADR:000A BUS:FF (011111111) Data:00 (000000000)                             
IR:00 [ins:0-LD  00011 mod:0-1110 bus-0000-ROM W:0 J:0 LD:0 ]                   
Y:00 (000000000) AC:00 (000000000) YL:1 XL:1 EH:1 EL:1 OL:1 LD:0 PL:1 PH:1      
                                                                                
PC:10 IR:00 [ins:0-LD  00011 mod:0-1110 bus-0000-ROM W:0 J:0 LD:0 ]             
D:FF AC:FF (011111111) X:00 Y:01                                                
---------------                                                                 
Clock cycle:13  ROM Lookup: IR:EC D:A                                           
                                                                                
ROM ADR:000B BUS:0A (000001010) Data:01 (000000001)                             
IR:EC [ins:7-BCC 01010 mod:3-1111 bus-0000-ROM W:0 J:1-cond LD:1 ]              
Y:00 (000000000) AC:00 (000000000) YL:1 XL:1 EH:1 EL:1 OL:1 LD:1 PL:0 PH:1      
                                                                                
PC:11 IR:EC [ins:7-BCC 01010 mod:3-1111 bus-0000-ROM W:0 J:1-cond LD:1 ]        
D:0A AC:FF (011111111) X:00 Y:01                                                
---------------                                                                 
Clock cycle:14  ROM Lookup: IR:69 D:0                                           
                                                                                
ROM ADR:000A BUS:FF (011111111) Data:00 (000000000)                             
IR:00 [ins:0-LD  00011 mod:0-1110 bus-0000-ROM W:0 J:0 LD:0 ]                   
Y:00 (000000000) AC:00 (000000000) YL:1 XL:1 EH:1 EL:1 OL:1 LD:0 PL:1 PH:1      
                                                                                
PC:10 IR:00 [ins:0-LD  00011 mod:0-1110 bus-0000-ROM W:0 J:0 LD:0 ]             
D:FF AC:FF (011111111) X:00 Y:01                                                
---------------                                                                 

I'll attach my Arduino program on the off-change anybody spots my mistake.

I'll continue tomorrow when I'm more awake ;-)
Attachments
gigatron_test.txt
(11.55 KiB) Downloaded 3 times

User avatar
marcelk
Posts: 252
Joined: 13 May 2018, 08:26

Re: Assembling Gigatron the hard way

Post by marcelk » 28 Apr 2019, 16:02

From the source (Core/ROMv3.py):

Code: Select all

# Simple RAM test and size check by writing to [1<<n] and see if [0] changes.
ld(1);                          C('RAM test and count')
label('.countMem0')
st([memSize], Y)
ld(255)
xora([Y,0])
st([Y,0])                       # Test if we can change and read back ok
st([0])                         # Preserve (inverted) memory value in [0]
xora([Y,0])
bne(pc())                       # Just hang here on apparent RAM failure
ld(255)
xora([Y,0])
st([Y,0])
xora([0])
beq('.countMem1')               # Wrapped and [0] changed as well
ld([memSize])
bra('.countMem0')
adda(AC)
label('.countMem1')
As you didn't paste the adda instruction after the last branch instruction, my first question is if you're aware of the branch delay slot? The instruction behind every jump instruction gets executed before the jump takes effect. Walter explains this in the presentation on how the Gigatron works. [Edit: fixed link]

pythag
Posts: 21
Joined: 21 Apr 2019, 20:29

Re: Assembling Gigatron the hard way

Post by pythag » 28 Apr 2019, 16:06

I've fixed the somewhat obvious error in my Arduino code (it was in the bit that simulates the ram space in the Arduino).

Attached is the updated code just for completeness.

The simulation now passes that sticking point in the code, and handily prints out what the various control outputs should be on the BCC cycle:

Code: Select all

Reset
Clock cycle:0
ROM ADR:0000 BUS:00 (000000000) Data:00 (000000000)
IR:00 [ins:0-LD  00011 mod:0-1110 bus-0000-ROM W:0 J:0 LD:0 ]
Y:00 (000000000) AC:00 (000000000) YL:1 XL:1 EH:1 EL:1 OL:1 LD:0 PL:1 PH:1

Clock cycle:1  ROM Lookup: IR:0 D:0

ROM ADR:0001 BUS:00 (000000000) Data:00 (000000000)
IR:00 [ins:0-LD  00011 mod:0-1110 bus-0000-ROM W:0 J:0 LD:0 ]
Y:00 (000000000) AC:00 (000000000) YL:1 XL:1 EH:1 EL:1 OL:1 LD:0 PL:1 PH:1

PC:1 IR:00 [ins:0-LD  00011 mod:0-1110 bus-0000-ROM W:0 J:0 LD:0 ]
D:00 AC:00 (000000000) X:00 Y:00
YL:1 XL:1 EH:1 EL:1 OL:1 LD:0 PL:1 PH:1 CO:0 AC7:0                              
---------------                                                                 
Clock cycle:2  ROM Lookup: IR:18 D:80                                           
                                                                                
ROM ADR:0002 BUS:80 (010000000) Data:20 (000100000)                             
IR:18 [ins:0-LD  00011 mod:6-1101 bus-0000-ROM W:0 J:0 LD:1 ]                   
Y:00 (000000000) AC:00 (000000000) YL:1 XL:1 EH:1 EL:1 OL:0 LD:1 PL:1 PH:1      
                                                                                
PC:2 IR:18 [ins:0-LD  00011 mod:6-1101 bus-0000-ROM W:0 J:0 LD:1 ]              
D:80 AC:00 (000000000) X:00 Y:00                                                
YL:1 XL:1 EH:1 EL:1 OL:0 LD:1 PL:1 PH:1 CO:0 AC7:0                              
---------------                                                                 
Clock cycle:3  ROM Lookup: IR:18 D:C0                                           
                                                                                
ROM ADR:0003 BUS:C0 (011000000) Data:20 (000100000)                             
IR:18 [ins:0-LD  00011 mod:6-1101 bus-0000-ROM W:0 J:0 LD:1 ]                   
Y:00 (000000000) AC:00 (000000000) YL:1 XL:1 EH:1 EL:1 OL:0 LD:1 PL:1 PH:1      
                                                                                
PC:3 IR:18 [ins:0-LD  00011 mod:6-1101 bus-0000-ROM W:0 J:0 LD:1 ]              
D:C0 AC:00 (000000000) X:00 Y:00                                                
YL:1 XL:1 EH:1 EL:1 OL:0 LD:1 PL:1 PH:1 CO:0 AC7:0                              
---------------                                                                 
Clock cycle:4  ROM Lookup: IR:0 D:1                                             
                                                                                
ROM ADR:0004 BUS:01 (000000001) Data:00 (000000000)                             
IR:00 [ins:0-LD  00011 mod:0-1110 bus-0000-ROM W:0 J:0 LD:0 ]                   
Y:00 (000000000) AC:00 (000000000) YL:1 XL:1 EH:1 EL:1 OL:1 LD:0 PL:1 PH:1      
                                                                                
PC:4 IR:00 [ins:0-LD  00011 mod:0-1110 bus-0000-ROM W:0 J:0 LD:0 ]              
D:01 AC:00 (000000000) X:00 Y:00                                                
YL:1 XL:1 EH:1 EL:1 OL:1 LD:0 PL:1 PH:1 CO:0 AC7:0                              
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Clock cycle:5  ROM Lookup: IR:D6 D:1                                            
                                                                                
ROM ADR:0005 BUS:81 (010000001) Data:22 (000100010)                             
IR:D6 [ins:6-ST  11111 mod:5-1111 bus-0010-AC  W:1 J:0 LD:1 ]                   
Y:00 (000000000) AC:00 (000000000) YL:0 XL:0 EH:1 EL:1 OL:1 LD:1 PL:1 PH:1      
                                                                                
PC:5 IR:D6 [ins:6-ST  11111 mod:5-1111 bus-0010-AC  W:1 J:0 LD:1 ]              
D:01 AC:01 (000000001) X:00 Y:00                                                
YL:0 XL:0 EH:1 EL:1 OL:1 LD:1 PL:1 PH:1 CO:0 AC7:0                              
---------------                                                                 
Clock cycle:6  ROM Lookup: IR:0 D:FF                                            
                                                                                
ROM ADR:0006 BUS:FF (011111111) Data:08 (000001000)                             
IR:00 [ins:0-LD  00011 mod:0-1110 bus-0000-ROM W:0 J:0 LD:0 ]                   
Y:00 (000000000) AC:00 (000000000) YL:1 XL:1 EH:1 EL:1 OL:1 LD:0 PL:1 PH:1      
                                                                                
Writing 1 to address 1                                                          
PC:6 IR:00 [ins:0-LD  00011 mod:0-1110 bus-0000-ROM W:0 J:0 LD:0 ]              
D:FF AC:01 (000000001) X:00 Y:01                                                
YL:1 XL:1 EH:1 EL:1 OL:1 LD:0 PL:1 PH:1 CO:0 AC7:0                              
---------------                                                                 
Clock cycle:7  ROM Lookup: IR:69 D:0                                            
                                                                                
ROM ADR:0007 BUS:FF (011111111) Data:20 (000100000)                             
IR:69 [ins:3-XOR 01001 mod:2-0110 bus-0001-RAM W:0 J:0 LD:0 ]                   
Y:00 (000000000) AC:00 (000000000) YL:1 XL:1 EH:0 EL:1 OL:1 LD:0 PL:1 PH:1      
                                                                                
PC:7 IR:69 [ins:3-XOR 01001 mod:2-0110 bus-0001-RAM W:0 J:0 LD:0 ]              
D:00 AC:FF (011111111) X:00 Y:01                                                
YL:1 XL:1 EH:0 EL:1 OL:1 LD:0 PL:1 PH:1 CO:0 AC7:1                              
---------------                                                                 
Clock cycle:8  ROM Lookup: IR:CA D:0                                            
                                                                                
ROM ADR:0008 BUS:80 (010000000) Data:20 (000100000)                             
IR:CA [ins:6-ST  11111 mod:2-0110 bus-0010-AC  W:1 J:0 LD:1 ]                   
Y:00 (000000000) AC:00 (000000000) YL:1 XL:1 EH:0 EL:1 OL:1 LD:1 PL:1 PH:1      
                                                                                
Read uninit from 256                                                            
PC:8 IR:CA [ins:6-ST  11111 mod:2-0110 bus-0010-AC  W:1 J:0 LD:1 ]              
D:00 AC:00 (000000000) X:00 Y:01                                                
YL:1 XL:1 EH:0 EL:1 OL:1 LD:1 PL:1 PH:1 CO:0 AC7:0                              
---------------                                                                 
Clock cycle:9  ROM Lookup: IR:C2 D:0                                            
                                                                                
ROM ADR:0009 BUS:80 (010000000) Data:00 (000000000)                             
IR:C2 [ins:6-ST  11111 mod:0-1110 bus-0010-AC  W:1 J:0 LD:1 ]                   
Y:00 (000000000) AC:00 (000000000) YL:1 XL:1 EH:1 EL:1 OL:1 LD:1 PL:1 PH:1      
                                                                                
Writing 0 to address 256                                                        
PC:9 IR:C2 [ins:6-ST  11111 mod:0-1110 bus-0010-AC  W:1 J:0 LD:1 ]              
D:00 AC:00 (000000000) X:00 Y:01                                                
YL:1 XL:1 EH:1 EL:1 OL:1 LD:1 PL:1 PH:1 CO:0 AC7:0                              
---------------                                                                 
Clock cycle:10  ROM Lookup: IR:69 D:0                                           
                                                                                
ROM ADR:000A BUS:80 (010000000) Data:38 (000111000)                             
IR:69 [ins:3-XOR 01001 mod:2-0110 bus-0001-RAM W:0 J:0 LD:0 ]                   
Y:00 (000000000) AC:00 (000000000) YL:1 XL:1 EH:0 EL:1 OL:1 LD:0 PL:1 PH:1      
                                                                                
Writing 0 to address 0                                                          
PC:10 IR:69 [ins:3-XOR 01001 mod:2-0110 bus-0001-RAM W:0 J:0 LD:0 ]             
D:00 AC:00 (000000000) X:00 Y:01                                                
YL:1 XL:1 EH:0 EL:1 OL:1 LD:0 PL:1 PH:1 CO:0 AC7:0                              
---------------                                                                 
Clock cycle:11  ROM Lookup: IR:EC D:A                                           
                                                                                
ROM ADR:000B BUS:0A (000001010) Data:2B (000101011)                             
IR:EC [ins:7-BCC 01010 mod:3-1111 bus-0000-ROM W:0 J:1-cond LD:1 ]              
Y:00 (000000000) AC:00 (000000000) YL:1 XL:1 EH:1 EL:1 OL:1 LD:1 PL:0 PH:1      
                                                                                
Read 0 from 256                                                                 
PC:11 IR:EC [ins:7-BCC 01010 mod:3-1111 bus-0000-ROM W:0 J:1-cond LD:1 ]        
D:0A AC:00 (000000000) X:00 Y:01                                                
YL:1 XL:1 EH:1 EL:1 OL:1 LD:1 PL:0 PH:1 CO:0 AC7:0                              
---------------                                                                 
Clock cycle:12  ROM Lookup: IR:69 D:0                                           
                                                                                
ROM ADR:000A BUS:FF (011111111) Data:08 (000001000)                             
IR:00 [ins:0-LD  00011 mod:0-1110 bus-0000-ROM W:0 J:0 LD:0 ]                   
Y:00 (000000000) AC:00 (000000000) YL:1 XL:1 EH:1 EL:1 OL:1 LD:0 PL:1 PH:1      
                                                                                
PC:12 IR:00 [ins:0-LD  00011 mod:0-1110 bus-0000-ROM W:0 J:0 LD:0 ]             
D:FF AC:00 (000000000) X:00 Y:01                                                
YL:1 XL:1 EH:1 EL:1 OL:1 LD:0 PL:1 PH:1 CO:0 AC7:0                              
---------------                                                                 
Clock cycle:13  ROM Lookup: IR:EC D:A                                           
                                                                                
ROM ADR:000B BUS:0A (000001010) Data:2B (000101011)                             
IR:EC [ins:7-BCC 01010 mod:3-1111 bus-0000-ROM W:0 J:1-cond LD:1 ]              
Y:00 (000000000) AC:00 (000000000) YL:1 XL:1 EH:1 EL:1 OL:1 LD:1 PL:0 PH:1      
                                                                                
PC:13 IR:69 [ins:3-XOR 01001 mod:2-0110 bus-0001-RAM W:0 J:0 LD:0 ]             
D:00 AC:FF (011111111) X:00 Y:01                                                
YL:1 XL:1 EH:0 EL:1 OL:1 LD:0 PL:1 PH:1 CO:0 AC7:1                              
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So now the control signals match what I measure on that cycle on the breadboard:

Measured:
YL:1 XL:1 EH:1 EL:1 OL:1 LD:1 PL:0 PH:1
Simulated:
YL:1 XL:1 EH:1 EL:1 OL:1 LD:1 PL:0 PH:1 CO:0 AC7:0

The important part is that PL matches the simulated output - this is what controls the jump.... So, why is it jumping??? I'll dig further...
Attachments
gigatron_test.txt
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