Another Gigatron Instruction Set Question.

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Another Gigatron Instruction Set Question.

Post by Martin_H » 01 Apr 2019, 22:51

Some aspects of the Gigatron remind me of the 6502, which shouldn't be a shock since they're both eight bit CPU's with three registers. One similarity is that it is possible to load X or Y with a load instruction, or to move a value from the accumulator into them. For example, I think this:

ld [$17] ; load AC with RAM test and count
st [$17],y ; store AC into y (tay on the 6502)

loads y with the value in ac, and the [$17] is basically ignored, while this:

ld [$17],y ; load contents of $17 into y.

directly loads the contents of $17 into Y.

Is my understanding correct?

Given that this kind of duplicates functionality between load and store. I'm curious if this fell out of the design for free, or was effort required to include it? if you omitted one of these modes could you have re-purposed an addressing mode for another purpose?

Register shift instructions are handy, and I think you can shift left by adding the accumulator to the accumulator, but I'm not sure how a right shift is achieved.

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Re: Another Gigatron Instruction Set Question.

Post by marcelk » 02 Apr 2019, 06:32

On 1:

For moving AC to X, I would use this:

Code: Select all

ld ac,x 
  1. It puts AC on the bus,
  2. lets the bus value pass through the ALU to the result bus unchanged, and
  3. lets X take the value from the result bus.
On 2:

The secondary destination, X or Y, in some store opcodes is a happy little accident. Store operations really don't have different addressing modes from load or ALU commands: their mode decoding share the same circuitry. But modes tie memory addressing and the result register together in some hardwired ways: one result register (AC, X, Y or OUT) is always part of the mode, and typically you don't want to modify registers while writing to RAM... We needed a solution for this as otherwise we wouldn't have very useable store instructions at all. As it turns out you can have any memory addressing mode available for store instructions if you just block AC and OUT when writing to RAM. In the schematic, two OR gates do that:

Screenshot 2019-04-02 at 01.52.36.png
Screenshot 2019-04-02 at 01.52.36.png (172.11 KiB) Viewed 733 times

With this setup, store instructions have all 5(*) memory addressing modes available. From there, there was no reason to mute X and Y in the same way as well. That spares us from adding 2 more OR gates. Now these unblocked combinations turn out to be quite useful by themselves, and this was unintentional. They copy AC to X (or Y) while also doing a memory write to the zero-page.

About your example:

Code: Select all

st [$17],y
This does two things in the same cycle: write AC to memory location $17, and also write AC to register Y.

More about their origin here: ... ed-opcodes

(*) "all 6 modes" is a typo in the schematic. We have [D], [X], [Y,D], [Y,X] and [Y,X++].

On 3:

Hardware right-shift isn't there because it slows down the ALU and it costs 2 more chips, while it isn't really missed. It sure helps that pixels are byte addressable instead of bitmapped, so there isn't a lot of shifting going on in graphics handling. Two common cases for right-shift are handled by RAM tables as follows:

Code: Select all

; AC >>= 7
anda $80,x
ld   [x]

Code: Select all

; AC >>= 2
ld   $07,y
ora  $03,x
ld   [y,x]
P.S: We have an unambiguous instruction set definition in C: gtemu.c

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Re: Another Gigatron Instruction Set Question.

Post by Martin_H » 02 Apr 2019, 22:01

Thanks for the reply and the documentation pointers. The ROM code makes much more sense once you know that store can writes to ram and a register in a single instruction.

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