New form factor Gigatron.

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Joined: 17 May 2018, 07:17

New form factor Gigatron.

Post by monsonite » 04 May 2019, 20:00

Hi All,

During the life cycle of a computer, - it is not uncommon for it to undergo a series of design changes - mainly to reduce costs or to take advantage of new technology.

The classic example of this metamorphosis is the PDP-8 minicomputer, which was conceived in the era of DTL (diode transistor logic) and over several design iterations and 10 years, took full advantage of the new, cheaper TTL devices.

I have been trying to push the existing Gigatron to the limits of its operation by using 74Fxxx TTL and running with a 13MHz clock. Marcel has an experimental board that looks like it will run at 15MHz.

However, running at these higher clock frequencies, pushes the current design to it's limits - and these limits appear like a cliff edge: Tetris will run perfectly happily at 13MHz on my machine, but Mandelbrot and Tiny BASIC regularly crash.

In order to improve the design so that it works reliably at higher clock speeds it is necessary to move up to a 4 layer printed circuit board, that has much better power distribution in the form of ground and power planes, and shorter signal paths.

The standard Gigatron was designed for ease of home construction, and the pcb has generous track widths and clearances.

This constructor friendly design not only meets its design criteria for a 6.25MHz clock - but remarkably there is sufficient margin to support twice that frequency.

However, the design requires the databus to reach several parts of the circuit, and on the large pcb, this results in the databus travelling almost 3/4 of the way around the pcb - all the way from the keyboard input, down the right side, across the bottom, and up the left side to the Bit 3 of the ALU - about 500 - 600 mm in total.

This weekend I have been looking to see if there is a better logical layout for the pcb - which helps to minimise the length of the data bus and the ALU results bus. The first step of this process was to transcribe the KiCAD schematics into EagleCAD ( as that is what I have at home) so that I could model the design and see if there were any easy improvements to make.

The first thing was to change the databus from "La Peripherique" to the central highway - and have it run straight down the centre of the board. This shortens it to about 200mm.

The next thing was to juggle the various registers such as X, Y, D and IR so that thy are as close as possible to the circuitry that they feed.

Another consideration was to include the proposed expansion components - and have a general purpose expansion connector on the back of the pcb. As a result - I have the whole design on a pcb just 200mm x120mm.

As there are so many ways of laying out a design, I will put the Eagle schematics on Github - so others can access the design and try their own layout. It's easy to change from a through hole design to a sufrface mount design from within the Eagle CAD environment.

Posts: 36
Joined: 17 May 2018, 07:17

Re: New form factor Gigatron.

Post by monsonite » 05 May 2019, 17:41

Hi All,

Attached is a PDF giving an overview of the Gigatron design.

I have hypothetically split the design into two roughly equal parts, loosely called "ALU" and "Memory" and then placed the sub-systems between these "camps" so as to minimise the number of signals that have to pass between them.

This shows that it would be possible to separate the two parts with just the data bus, the ALU result bus, and 11 control signals separating them. If you really wanted, you could follow this scheme and split the Gigatron onto two smaller pcbs with just a 30 pin connector joining them.

This exercise also highlighted that there are eight, 8-bit signal buses ALU, AC, Data Bus, D, IR, Out, X, Y which need to be routed. Additionally, minor buses such as the 5 signals that have to be routed to each of the eight 74HCT153 multiplexers in the ALU. Some signal buses, like the ROM address bus only pass between two components - the PC and the ROM, and whilst clearly should be kept as short as possible, reinforced the reasons to keep some components tightly grouped.

When laying out the pcb it is necessary to juggle the various registers such as X, Y, D and IR so that thy are as close as possible to the circuitry that they feed. This is the hardest part, because although D and IR are closely attached to the ROM, the data register must also be close to the data bus and the memory address unit. Achieving this on the board makes for some tricky layout.

The X and Y registers must also be close to the memory address unit, but the Y-bus must also feed the program counter. In each case there are conflicting requirements in the geographical location of the various subsections - that makes layout all the more complex.

Edit - I have split the PDFs and images into two A3 landscape sheets for better resolution
Gigatron ALU Section - A3 Landscape
(24.74 KiB) Downloaded 8 times
Gigatron Memory Section - A3 Landscape
(29.12 KiB) Downloaded 7 times
Gig_Memory_A3L.png (43.36 KiB) Viewed 146 times
Gig_ALU_A3L.png (38.12 KiB) Viewed 146 times
Last edited by monsonite on 06 May 2019, 10:52, edited 1 time in total.

Posts: 29
Joined: 11 Apr 2019, 07:15
Location: Valladolid, Spain

Re: New form factor Gigatron.

Post by gesari » 05 May 2019, 21:01

I don't think a better layout will change the max clock frequency too much. Even if the data bus traces are 200mm shorter this length equals only to about 1.3ns propagation delay (wave velocity in tracks is more or less 1/2 the speed of light in vacuum). For a 15MHz clock this delay is only a 2% of the cycle time.
On the other hand a 4 layer layout can result in higher parasitic capacitances than a bare 2-layer PCB (for the same trace length).

Posts: 36
Joined: 17 May 2018, 07:17

Re: New form factor Gigatron.

Post by monsonite » 06 May 2019, 18:53

Hi All,

After a few hours with EagleCAD, I have a proof of concept, reduced format pcb layout. The size is 200 x 100 mm.

Power and ground planes are on the inner 2 layers, with all signals on the top or bottom layers.

I have included an 8-bit output port and an 8-bit input port - as per the proposed expansion scheme. These appear on a 2x10 way header at the rear of the pcb.

The RAM bus (address and data) is brought out to a 2 x 20 way connnector on the right edge of the pcb. Blinkenlights and sound have also been brought out to a connector on the edge of the pcb.

The files for the schematic and board can be found on Github here:

Latest version is Gig_14

Reduced Size Gigatron 200mm x100mm 4 layer pcb
Gig_14.JPG (258.72 KiB) Viewed 128 times

If you use KiCAD - the Eagle schematic file may be imported. If you don't have either EagleCAD or KiCAD you might consider a cloud-based CAD package called EasyEDA - which also allows EagleCAD files to be loaded and modified and gerbers etc to be created. Unlike Eagle CAD Lite it has no immediate restriction to board size or number of layers.

Below is the 3D view of the pcb - generated in EasyEDA.
3D view of bare pcb
gigatron_3D.JPG (242.03 KiB) Viewed 107 times

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