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New form factor Gigatron.

Posted: 04 May 2019, 20:00
by monsonite
Hi All,

During the life cycle of a computer, - it is not uncommon for it to undergo a series of design changes - mainly to reduce costs or to take advantage of new technology.

The classic example of this metamorphosis is the PDP-8 minicomputer, which was conceived in the era of DTL (diode transistor logic) and over several design iterations and 10 years, took full advantage of the new, cheaper TTL devices.

I have been trying to push the existing Gigatron to the limits of its operation by using 74Fxxx TTL and running with a 13MHz clock. Marcel has an experimental board that looks like it will run at 15MHz.

However, running at these higher clock frequencies, pushes the current design to it's limits - and these limits appear like a cliff edge: Tetris will run perfectly happily at 13MHz on my machine, but Mandelbrot and Tiny BASIC regularly crash.

In order to improve the design so that it works reliably at higher clock speeds it is necessary to move up to a 4 layer printed circuit board, that has much better power distribution in the form of ground and power planes, and shorter signal paths.

The standard Gigatron was designed for ease of home construction, and the pcb has generous track widths and clearances.

This constructor friendly design not only meets its design criteria for a 6.25MHz clock - but remarkably there is sufficient margin to support twice that frequency.

However, the design requires the databus to reach several parts of the circuit, and on the large pcb, this results in the databus travelling almost 3/4 of the way around the pcb - all the way from the keyboard input, down the right side, across the bottom, and up the left side to the Bit 3 of the ALU - about 500 - 600 mm in total.

This weekend I have been looking to see if there is a better logical layout for the pcb - which helps to minimise the length of the data bus and the ALU results bus. The first step of this process was to transcribe the KiCAD schematics into EagleCAD ( as that is what I have at home) so that I could model the design and see if there were any easy improvements to make.

The first thing was to change the databus from "La Peripherique" to the central highway - and have it run straight down the centre of the board. This shortens it to about 200mm.

The next thing was to juggle the various registers such as X, Y, D and IR so that thy are as close as possible to the circuitry that they feed.

Another consideration was to include the proposed expansion components - and have a general purpose expansion connector on the back of the pcb. As a result - I have the whole design on a pcb just 200mm x120mm.

As there are so many ways of laying out a design, I will put the Eagle schematics on Github - so others can access the design and try their own layout. It's easy to change from a through hole design to a sufrface mount design from within the Eagle CAD environment.

Re: New form factor Gigatron.

Posted: 05 May 2019, 17:41
by monsonite
Hi All,

Attached is a PDF giving an overview of the Gigatron design.

I have hypothetically split the design into two roughly equal parts, loosely called "ALU" and "Memory" and then placed the sub-systems between these "camps" so as to minimise the number of signals that have to pass between them.

This shows that it would be possible to separate the two parts with just the data bus, the ALU result bus, and 11 control signals separating them. If you really wanted, you could follow this scheme and split the Gigatron onto two smaller pcbs with just a 30 pin connector joining them.

This exercise also highlighted that there are eight, 8-bit signal buses ALU, AC, Data Bus, D, IR, Out, X, Y which need to be routed. Additionally, minor buses such as the 5 signals that have to be routed to each of the eight 74HCT153 multiplexers in the ALU. Some signal buses, like the ROM address bus only pass between two components - the PC and the ROM, and whilst clearly should be kept as short as possible, reinforced the reasons to keep some components tightly grouped.

When laying out the pcb it is necessary to juggle the various registers such as X, Y, D and IR so that thy are as close as possible to the circuitry that they feed. This is the hardest part, because although D and IR are closely attached to the ROM, the data register must also be close to the data bus and the memory address unit. Achieving this on the board makes for some tricky layout.

The X and Y registers must also be close to the memory address unit, but the Y-bus must also feed the program counter. In each case there are conflicting requirements in the geographical location of the various subsections - that makes layout all the more complex.

Edit - I have split the PDFs and images into two A3 landscape sheets for better resolution
Gigatron ALU Section - A3 Landscape
(24.74 KiB) Downloaded 250 times
Gigatron Memory Section - A3 Landscape
(29.12 KiB) Downloaded 249 times
Gig_Memory_A3L.png (43.36 KiB) Viewed 6602 times
Gig_ALU_A3L.png (38.12 KiB) Viewed 6602 times

Re: New form factor Gigatron.

Posted: 05 May 2019, 21:01
by gesari
I don't think a better layout will change the max clock frequency too much. Even if the data bus traces are 200mm shorter this length equals only to about 1.3ns propagation delay (wave velocity in tracks is more or less 1/2 the speed of light in vacuum). For a 15MHz clock this delay is only a 2% of the cycle time.
On the other hand a 4 layer layout can result in higher parasitic capacitances than a bare 2-layer PCB (for the same trace length).

Re: New form factor Gigatron.

Posted: 06 May 2019, 18:53
by monsonite
Hi All,

After a few hours with EagleCAD, I have a proof of concept, reduced format pcb layout. The size is 200 x 100 mm.

Power and ground planes are on the inner 2 layers, with all signals on the top or bottom layers.

I have included an 8-bit output port and an 8-bit input port - as per the proposed expansion scheme. These appear on a 2x10 way header at the rear of the pcb.

The RAM bus (address and data) is brought out to a 2 x 20 way connnector on the right edge of the pcb. Blinkenlights and sound have also been brought out to a connector on the edge of the pcb.

The files for the schematic and board can be found on Github here:

Latest version is Gig_14

Reduced Size Gigatron 200mm x100mm 4 layer pcb
Reduced Size Gigatron 200mm x100mm 4 layer pcb
Gig_14.JPG (258.72 KiB) Viewed 6584 times

If you use KiCAD - the Eagle schematic file may be imported. If you don't have either EagleCAD or KiCAD you might consider a cloud-based CAD package called EasyEDA - which also allows EagleCAD files to be loaded and modified and gerbers etc to be created. Unlike Eagle CAD Lite it has no immediate restriction to board size or number of layers.

Below is the 3D view of the pcb - generated in EasyEDA.
3D view of bare pcb
3D view of bare pcb
gigatron_3D.JPG (242.03 KiB) Viewed 6563 times

Re: New form factor Gigatron.

Posted: 22 Jan 2020, 04:34
by GigaMike
I am new to Gigatron. This is an interesting thread. I am appended to it because I am looking at monsonite's Eagle CAD files. I am very familiar with Eagle.

First I had to fix a number of problems and issues on the Gig_14 version. It would be helpful if Monsonite can verify that he did the same things.
  1. Fixed schematic errors/warnings such as overlapping nets or missing junctions
  2. Changed decade counter 74HCT160 to 16 bit counter 74HCT161 for U29/U30 (X register)
  3. Connected "H" and "L" nets to VCC and GND
  4. Renamed CLK to CLK1 on U3-U6
  5. Added more 0.1uF caps for every IC
  6. Changed order of AR0-AR3 outputs on U15 as reversed
  7. Assigned values to resistors, caps, and diodes. I choose the BAT54 for the common anode SMD diode.
Second I converted everything to SMD parts and worked on getting the PCB as small as possible. JLCPCB has a special of $29 for ten 100mm x 100mm 4 layer boards. Because the surface area of all of the parts exceeds the PCB, some of the SMD chips are placed on the "solder" side. I have a proof of concept where I was able to layout a 4 layer board with separate GND and VCC planes.

Third I made some enhancements. Monsonite already included much of the expansion bus circuitry but more things were needed as follows:
  1. Changed everything to 74F00 series chips except for 14, 139, 540, 595 which do not have 74F versions.
  2. Upgraded ROM and RAM part numbers to have better speeds. There is a 35nS ROM MC27C1024 but it may not be needed.
  3. Per this append, I have added clock and diode resistor changes to support 12.5 MHz. I have the facility to use 0R resistors to choose where CLK2 is taken from (pin 10 or pin 8 of U1).
  4. Made sure that the cathodes of unused diodes are pulled high.
  5. Removed extension header as there is not really room for 2x20 header for address and data lines.
  6. Added audio output circuitry.
  7. Added ATTiny85 and mini DIN6 PS/2 keyboard socket so the board has a built in Pluggy.
  8. Added more comments to the schematic (copied over from KiCAD)
  9. Improved some of the schematic layout to make things clearer
I have more to do with improving the layout of the components and getting to hand-routing the board rather than using the autorouter tool. I did find the autorouter useful for creating the VCC and GND vias to the respective planes. Eventually I plan to submit a pull request to Monsonite's Github repository.

Is anyone interested in this type of PCB? 100mm x 100mm using 1.27mm pitch ICs and 0603 discrete components? I keep the socket for the ROM of course.

Re: New form factor Gigatron.

Posted: 23 Jan 2020, 12:41
by bmwtcu
Great job Mike! The last time I checked with Ken late 2019, he had not actually ordered the rev 14 boards because he had moved on to the Suite-16.

Re: New form factor Gigatron.

Posted: 02 Jun 2020, 01:12
by frob
Ken / Mike,
this is really great work! i'm very interested in this Gigatron "branch", and would like to try to help develop it further.
Has either of you built / tested one of these boards yet ? i'd be very interested to hear how that is going.

Mike if you have PCB's i'd be interested in getting one and helping to test it out.
If not, i'd like to add my own tweaks to improve speeds and reliable high-speed operation, maybe merge the ROM in-circuit debug, expand memory to 512K, add support for high-rez video DMA add-on, etc.
I'd prefer to start from an SMT base version like yours, if you are willing to share your source, i'd love to build on them.
i've been looking into whats available for very high speed logic, that's compatible with more modern / available high-speed SRAM (3V) .
seems most can be found in VHC /LVC / LCX logic families that's actually faster than 5V 74F at 3V, except for the adders, which will have to remain in 5V 74F (or maybe 74AC @ 3V, and pay a small speed penalty in exchange for easier interfacing to other 3V logic) - so i'm thinking about doing a mixed-voltage version, most of it at 3V, adders and a few other exceptions at 5V. Total power draw should be much close to the original Gigatron.


Re: New form factor Gigatron.

Posted: 14 Jun 2020, 19:38
by GigaMike
I started the PCB layout in Eagle. It is quite challenge to get everything to fit into 100mm x 100mm even with 4 layer PCB and components end up on both sides. This size is important because several companies have specials at this price for low volume.

However I have not made further progress and then covid-19 hit. This was always a side project for me and I am been concentrating on my other hobbies more since mid-March.

I'm not a fan of the mixed-voltage idea BTW.

Re: New form factor Gigatron.

Posted: 16 Jun 2020, 00:21
by frob
I know how challenging that can be. I actually do this kind of stuff for a living, and have done some insanely high-density layouts over the last bunch of years. Often I've had to rip up and reroute large areas of a board in order to squeeze in 'one last track' on a very dense board. Over the year's I've figured out several tricks to get tightly packed boards to route out successfully, without compromising EMI compliance, signal integrity etc.. I must be a masochist as i actually enjoy the layout phase of design work. Some people like to do crosswords, others enjoy 10,000 piece jigsaw puzzles, but on a rainy day i'm more likely to be working on a 484-ball BGA fanout or similar :mrgreen:

I've also got other priorities this summer (my main "hobby" these days is trying to rebuild our century old house before my parental leave expires) so i can't dedicate a whole lot of time to Gigatron hacking, but maybe an hour or 3 per week is manageable.
If you like i can take a stab at trying to complete your layout (no design changes) just so we can order boards and see if it works. I'm pretty sure i can import Eagle design files more or less intact into Altium.
That's a great deal on PCB's by the way, I've never ordered from them but i'm keen to see what kind of quality you get for that price, and stainless stencils for $10 CAD is a steal too. They say they do 5mil trace/space standard, that's quite good for a low-cost board house, and should me more than good enough for this design.

I'm curious what about the mixed voltage idea you find particularly unenchanting?
that's just something i'd like to be able to experiment with to try to squeeze every last MHz out of the design (while giving a little more choice on sourcing the parts), but there's no reason a board couldn't be designed to allow either 5V or 3.3V to the IC's in question (that's pretty easy), so you could build it either way...

Re: New form factor Gigatron.

Posted: 17 Jun 2020, 02:47
by GigaMike
While I don't do PCB layout for a living, I have created a number of densely packed boards when I creating breakout boards for Atmel microcontrollers. The smallest component was 0603 for hand-soldering. And I know exactly what you mean about moving traces 1 or 2 mil just to fit in another trace for better routing. Sometimes I would rough routing to "juggle" traces and then turn back on 45 degree traces and meticulously go through and eliminate each routing error. It took time but strangely cathartic - a bit like jigsaw puzzles I guess.

My problem with mixed voltages is that you may need to add level shifters (extra ICs) and it seems to deviate too much from TTL which has always been 5V in my mind.