dual ported SRAM for co-processing
Posted: 07 Jun 2019, 12:06
I was wondering if the 32 kb extension as proposed by Marcel could alternatively be used with dual-ported SRAM instead
This way two gigatrons side to side can have shared memory, share memory structures for high-speed I/O, using spinlocks to protect data structures,
and have truely bidirectional I/O with two 'threads' each running from their own ROM
IDT seems to be one of the only few selling dual-ported SRAM @ 5V, but price is above $50 but available in hand-solderable TQFN package
It does feature /busy outputs, which could be ignored for simplicity reasons, or think on some logic to suspend or stretch a clock of the other
unit while writing
Using a small FPGA to simulate such device might work too - Lattice has a few small FPGAs with third party OSS tools available - but the 5V barrier is a bit high - all I/0 would need to be levelshifted
are there other idea's to make a 'dual-core' 'transputer' like support feasible with 5 volt technology ?
cmpxchg
This way two gigatrons side to side can have shared memory, share memory structures for high-speed I/O, using spinlocks to protect data structures,
and have truely bidirectional I/O with two 'threads' each running from their own ROM
IDT seems to be one of the only few selling dual-ported SRAM @ 5V, but price is above $50 but available in hand-solderable TQFN package
It does feature /busy outputs, which could be ignored for simplicity reasons, or think on some logic to suspend or stretch a clock of the other
unit while writing
Using a small FPGA to simulate such device might work too - Lattice has a few small FPGAs with third party OSS tools available - but the 5V barrier is a bit high - all I/0 would need to be levelshifted
are there other idea's to make a 'dual-core' 'transputer' like support feasible with 5 volt technology ?
cmpxchg