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Re: 10MHz, 12.5MHz and Beyond!

Posted: 25 May 2021, 21:33
by Sugarplum
To go beyond a little past 12 Mhz, that is where you start to rethink other things.

Redesigning the ALU to use a carry-skip adder configuration would likely help because that would allow both carry possibilities to be calculated at the same time with a minor switching delay rather than calculating the nybbles in series. That adds only 2 more chips. Once you get to 20 Mhz, you'd likely need to make adders yourself using many of the fastest AND and XOR gates such as Drass is using in his 100 Mhz TTL/CMOS 6502 project. But that would not be 5v tolerant at all. Once you get really fast, you'd want to split the arithmetic and logic functions into 2 separate units. Or you could distribute the math/logic with even more chips where each operation has its own circuits.

Then you reach the idea of adding another pipeline. That would require a new ROM and inserting registers into the control lines to separate the control unit from the ALU. Theoretically, that should allow for up to 50% more speed, depending on how balanced your latencies are between the stages. By that point, your ROM will be the limiting factor.

When ROM becomes a limiting factor, one can add the fastest 16-bit SRAM and have a circuit to copy the ROM to the SRAM on boot and then execute out of the ROM shadow SRAM. So with a 3-stage pipeline and 40 ns SRAM shadowing the ROM, that would put you closer to 25 Mhz. If you are not afraid of 3.3v and lower voltages or SMTs, you might find 8-10 ns SRAM (with a theoretical maximum of 100-120 Mhz, depending on the other stages).

If one is not interested in native mode compatibility, they might be able to rework the ISA to help simplify the control unit. That would be incompatible with what we have, but you could still have vCPU compatibility. Finding a way around chaining decoders would be desirable. If you can't avoid that, then maybe one could borrow a cue from the carry-skip adder arrangement and calculate multiple values at the same time and use a "switch" (multiplexer) to put the correct one on the bus as determined by the earlier decoder.

Of course, the clock rate is not everything. Other speedups will be fruitful. The line repeater would allow you to use mode 4 all the time. Separating the video generation from the CPU would be helpful too. Doing that will increase performance at lower clock rates, but depending on how you do it, that could limit higher clock rates (unless you get more sophisticated with caches). More usable native opcodes would help gain speed through improving code density. Adding more registers and instructions that work with multiple data would speed up things, as would being able to run multiple instructions at the same time. More cores could help, but that depends on the software.

Re: 10MHz, 12.5MHz and Beyond!

Posted: 31 May 2021, 04:40
by ImmortanJoe
Hi. I've held off posting until I had the PCBs in my hands. They arrived today so I want to get started.

Given I just have the mainboard and pluggy, I'm left with the opportunity to put together the board how I see fit.

I was curious about the FLIR heat maps I saw on here. I'm a bit hazy on latency, but I wanted to know if it's only worthwhile uprating components that are being ran harder?

I'd like to do a modest clock increase if it's permissible. If so I might as well just buy those the right parts straight off.

I guess what I'm looking for is some help with a modified BOM?

Re: 10MHz, 12.5MHz and Beyond!

Posted: 05 Jun 2021, 11:12
by monsonite

I increased the clock frequency to 8MHz, just using the standard components, and I was still able to get a much compressed picture from my monitor.

I increased the frequency to 10MHz and although the monitor would no longer sync to this, the Blinkenlights still flashed confirming that the machine was still running.

I then swapped out almost all the chips for 74F (Fast) and got up to 12.5MHz.

Someone suggested using 74VHC series chips, as these have very low propagation time, but unfortunately not all are available, and not available in the DIL package.

I was happy to achieve 12.5MHz, and Marcel supplied me a special ROM with modified sync timings to cope with the doubled clock frequency.

Marcel also tried an experimental 4 layer pcb - which provided 5V power and ground planes for better power distribution and better EMC noise reduction. With this I believe he got up to about 15MHz.

Re: 10MHz, 12.5MHz and Beyond!

Posted: 05 Jun 2021, 16:48
by walter
I have the 15MHz version here. It has a different SRAM (AS7C256A-10JCN) that is not available in DIP28, so it uses a small SOJ-to-DIP adapter board. The ROM is a fast 27C1024 EEPROM (containing the special ROM v3y). CLK2 is not used, CLK1 is split off to CLK2. The caps (C1 and C2) in the pierce oscillator are removed. (The clock uses a 74HCT04). The PCB is a 4-layer version. Unfortunately, the KiCad files of the 4-layer version are lost. Dave from eevblog also made a quick&dirty version of a 4-layer board.

Re: 10MHz, 12.5MHz and Beyond!

Posted: 13 Jun 2021, 11:13
by monsonite

Marcel and I collaborated over the high speed version. I supplied the RAM on its adaptor pcb, the blank ROM and all of the 74F series ICs that were still available - in particular the 74F283 adders and 74F153 multiplexers to speed up the ALU. The counters in the Program Counter, X-reg and the data selectors in the MAU were also upgraded to 74F parts.

The other modification that might not be immediately obvious is that the pull-up resistors in the instruction decoder diode matrix were lowered to 600 ohms.

It's a tribute to Marcel's bullet-proof design that even the standard version would still run at 10MHz!

Re: 10MHz, 12.5MHz and Beyond!

Posted: 13 Jun 2021, 15:17
by walter
Thanks for the addition.