Re: Gigatron optimisation for a lite version?
Posted: 29 Jan 2020, 14:46
There's still only one databus - A and B is just which table of drivers will be driving the bus. Only one of those 8 drivers will be able to drive the bus at a time, but I don't have enough instruction bits to select all of them all of the time. So for example, I can't choose from the B set of drivers and the B set of destinations at the same time. Not everything can be a source to every destination. I may work on that some more.
The IR3 is an overlap which I need to clarify - it's only used when IR2=0. Again, I'm limited in instruction bits. So when I do a RAM read I only use two instruction bits. But when I do a RAM write I can use three. So I have 4 more ways of addressing the memory on a write. It's confusing so it's possible I may take it out. There's a lot to be said for simplicity. But it also gives more options for free.
I was planing on doing a lot of assembly macros to make up for the lack of ALU. I figure it's not very software friendly, but you have to give up something for a reduced cost, and this sacrifice is ease of programming. This is an easy trade for me since I'm an electrical engineer. And I don't know if I'd actually make this system.
The IR3 is an overlap which I need to clarify - it's only used when IR2=0. Again, I'm limited in instruction bits. So when I do a RAM read I only use two instruction bits. But when I do a RAM write I can use three. So I have 4 more ways of addressing the memory on a write. It's confusing so it's possible I may take it out. There's a lot to be said for simplicity. But it also gives more options for free.
I was planing on doing a lot of assembly macros to make up for the lack of ALU. I figure it's not very software friendly, but you have to give up something for a reduced cost, and this sacrifice is ease of programming. This is an easy trade for me since I'm an electrical engineer. And I don't know if I'd actually make this system.