A Gigatron Simulator for Learning Digital Logic.
Posted: 03 Aug 2021, 12:29
Hi All,
I have recently created a simulator of the Gigatron circuit, using H. Neeman's Digital Simulator - which is available on Github.
This simulator allows you to animate the TTL circuit and monitor the various signals as they switch. It allows you to single step through the instructions and watch how the instruction modifies the signals on the various buses and control lines.
I have created a "Front Panel" - shown below, which allows you to monitor the main buses and registers using multiple 7-segment displays. These allow you to view ROM Address, Instruction, Data, RAM Address, Output Register, Switch Inputs etc.
Whilst a real Gigatron produces a VGA display and audio, the intention of this simulator is to allow you to explore the architecture and instruction set of the machine. It also highlights the effect of the simple pipeline, where one instruction is being executed whilst the next is being fetched.
The design deviates a little from the real Gigatron - registers are mostly made from pairs of 4-bit 74xx173 as they have better arranged pins than the 8-bit 74xx377. Similarly 74xx240, 74xx244 and 74xx273 have been swapped out for more "bus friendly" '540, '541 and '574.
I am pleased to say that this morning I began debugging the design and it has executed its first code - a simple 16 byte routine from ROM, that sequences the Blinkenlights.
I have placed the design in my Github repository - but be aware that this is a first draft and is likely to evolve during the debugging phase:
https://github.com/monsonite/Gigatron-S ... /README.md
H Neeman's "Digital" simulator can be downloaded from here:
https://github.com/hneemann/Digital
With the main logic design in place, it is relatively simple to make changes. I am thinking of using a universal shift register for the accumulator to allow shift operations in hardware. I have also added a zero detector on the ALU output.
One of the advantages of the logic simulator is that you can easily make changes. The ALU could be replicated to make a 16-bit architecture for example.
This is a view of the whole design - which I have broken down into 6 manageable sections: X & Y registers and RAM, Front Panel, Program Counter and ROM, Control Unit, ALU-High and ALU Low.
I have recently created a simulator of the Gigatron circuit, using H. Neeman's Digital Simulator - which is available on Github.
This simulator allows you to animate the TTL circuit and monitor the various signals as they switch. It allows you to single step through the instructions and watch how the instruction modifies the signals on the various buses and control lines.
I have created a "Front Panel" - shown below, which allows you to monitor the main buses and registers using multiple 7-segment displays. These allow you to view ROM Address, Instruction, Data, RAM Address, Output Register, Switch Inputs etc.
Whilst a real Gigatron produces a VGA display and audio, the intention of this simulator is to allow you to explore the architecture and instruction set of the machine. It also highlights the effect of the simple pipeline, where one instruction is being executed whilst the next is being fetched.
The design deviates a little from the real Gigatron - registers are mostly made from pairs of 4-bit 74xx173 as they have better arranged pins than the 8-bit 74xx377. Similarly 74xx240, 74xx244 and 74xx273 have been swapped out for more "bus friendly" '540, '541 and '574.
I am pleased to say that this morning I began debugging the design and it has executed its first code - a simple 16 byte routine from ROM, that sequences the Blinkenlights.
I have placed the design in my Github repository - but be aware that this is a first draft and is likely to evolve during the debugging phase:
https://github.com/monsonite/Gigatron-S ... /README.md
H Neeman's "Digital" simulator can be downloaded from here:
https://github.com/hneemann/Digital
With the main logic design in place, it is relatively simple to make changes. I am thinking of using a universal shift register for the accumulator to allow shift operations in hardware. I have also added a zero detector on the ALU output.
One of the advantages of the logic simulator is that you can easily make changes. The ALU could be replicated to make a 16-bit architecture for example.
This is a view of the whole design - which I have broken down into 6 manageable sections: X & Y registers and RAM, Front Panel, Program Counter and ROM, Control Unit, ALU-High and ALU Low.