High resolution mode?

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tocksin
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Joined: 22 Jun 2018, 14:12

High resolution mode?

Post by tocksin » 10 Jul 2018, 17:08

I was thinking of ways to increase the resolution video output. Right now it takes one instruction per pixel, so you can't really optimize that. But I was thinking what if did two pixels per instruction? Maybe if we do a DDR (double-data-rate) trick by putting a 2:1 mux on the OUTPUT with the clock being the select line. So when the clock is high, it grabs the normal pin. Then when the clock is low, it switches to a second unused output pin.

Since there aren't enough pins on the output register to do this for all colors, we'd have a reduced color range for the high-res mode. I was thinking maybe the 74HCT157 would do the trick. We'd need 3 of the 2:1 muxes, but we'd have to use say output-pin 8 for both like the red and green. So this means the clock low colors would be white, black, blue, and yellow I think.

It would be nice to have this feature with an enable/disable too. Perhaps logical-AND the clock with another bit. I think maybe steal a control line from a blinkenlight on the XOUT register. This way you can have the full color low-res mode, and then switch to high-res mode where you'd only use 4 colors (or a weird 3bit/2bit color mode which could get some interesting dithering options)

The alternate solution would be to use the output-pin6 and get full hi-res color. But then that messes up the XOUT register. So what's your choice: full-color hi-res or LEDs/audio? I'd probably vote for LEDs/audio.

I haven't tried this yet, but thoughts?

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marcelk
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Re: High resolution mode?

Post by marcelk » 10 Jul 2018, 19:29

Your thinking is ingenious. Wouldn't you simply get 2 pixels of 8 possible colors each? We just split the 1x6 color outputs in 2x3 after all (no need to share a line?).

A minor detail is that the clock signal is currently asymmetric, with the second phase longer than the first. So that gives uneven pixels in the proposed scheme. That asymmetric clock is on purpose, but only so that we can remain compatible with slower SRAM than those currently shipped with the kit. The /WRITE pulse is derived from this: the longer we can make that pulse, the slower the SRAM we can use. Here you see the clock (probed at an inverted line BTW).

DS1Z_QuickPrint30.png
DS1Z_QuickPrint30.png (117.71 KiB) Viewed 1862 times

My expectation is that for the 55 ns SRAM in the kit, the clock can be made symmetric without SRAM problems, and then we get 320 equally sized pixels. One would expect this can simply be done by replacing the 74HCT04 with a 74HC04, because there the input levels are symmetric. HOWEVER, we did a LOT of testing with different clock circuits for the Gigatron one year ago, and for some reason we always experienced startup problems with the 74HC04. So this is something to look after. (Also, it would be nicer if there is a TTL alternative that works as well.)

tocksin
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Re: High resolution mode?

Post by tocksin » 10 Jul 2018, 23:26

Yes with 6 color outputs per 1 pixel we could reduce it to 3 color outputs per 2 pixels. It's still a color reduction when going to 320 pixels, but probably worth it to get to 40 characters per row for a text mode.

It may still work with an asymmetric clock. It depends on when the VGA monitor samples the input. Of course, then you would be faced with some monitors working and some not working. It would be easy enough to bread-board and try out tho!

tocksin
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Joined: 22 Jun 2018, 14:12

Re: High resolution mode?

Post by tocksin » 14 Jul 2018, 20:48

I'm thinking to get both the high-res and low-res modes, we could add a 2:1 analog multiplexer: 74HCT4053. We'd need two different resistor arrays, but this would be a simple solution.

Then we could pull a line from the blinkenlights to the select line. OR as a more advanced option - we could capture the D register with the HSYNC and make like a second XOUT register. Maybe use that to control peripherals or other low-speed devices along with the video mode.

https://www.digikey.com/product-detail/ ... 5-ND/38605

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marcelk
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Re: High resolution mode?

Post by marcelk » 14 Jul 2018, 22:47

The blinkenlights are free-to-use outputs. Three of them can drive a chain of shift registers.

Or capture AC with vSync for "XOUT2". Move the blinkenlights over to XOUT2 and have 4 more free output pins. Make the sound 8 bits on XOUT.

Or steal a bit from the sound...

Or use Y bit 7 to select resolution. Outside the pixel burst its value (0 or 1) doesn't matter (black = 000000 = 000:000 = black:black).

Many ideas to get a control bit...
It may still work with an asymmetric clock. It depends on when the VGA monitor samples the input.
They are sampling at 25.175 MHz or more, much faster than the Gigatron can generate. They won't snap to a 160 pixel (or 320 pixel) grid.

tocksin
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Joined: 22 Jun 2018, 14:12

Re: High resolution mode?

Post by tocksin » 15 Aug 2018, 20:08

I wonder if a 74HCT14 would oscillate closer to 50/50 duty cycle. It's still an inverter, but has Schmitt triggered inputs. If you haven't tried it, I will get some and see if there's any improvement.

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marcelk
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Re: High resolution mode?

Post by marcelk » 20 Aug 2018, 00:44

I don't have the 74HCT14, but we can easily order one when we're buying chips again. Another method is to start with a double clock of any kind and lead it through a D-flipflop to halve the frequency and balance the duty cycle. It will add a component, unless using something like the 74HCT4060.

HGMuller
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Re: High resolution mode?

Post by HGMuller » 18 Sep 2018, 19:07

It should be possible to symmetrize the signal presented to the mux select input by a circuit of some passive components: put a small capacitor between ground and that input, plus a pull-up resistor, and connect it through a (Schotky) diode to the clock source. The diode will discharge the capacitor much faster than the pull-up can charge it. This delays the rising edge.

gesari
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Re: High resolution mode?

Post by gesari » 19 Apr 2019, 09:27

I think the easiest way to get an 50% duty clock is to connect a 1k2 resistor in parallel with C2.
This will also lower the oscillation amplitude at the inverter input (pin 1) avoiding negative voltages.

And I see no problem with slow RAMs. Even the 70ns part has a write pulse width of 50ns, less than the 80ns of a symmetric clock. On the contrary, address lines have to be valid before the write pulse and they depend on the delay of the decoding logic, so I think it would be be good to have a longer high level for the clock.

Regards

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marcelk
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Re: High resolution mode?

Post by marcelk » 19 Apr 2019, 11:55

Indeed, tWP is shorter than the total write cycle time. On the breadboard prototype we had a symmetrical clock, because it was just a 25.175 MHz oscillator that got divided by a counter. That was before we switched to a more authentic oscillating circuit.

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