High resolution mode?

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Re: High resolution mode?

Post by marcelk » 05 Jul 2019, 17:48

We do have an inverted clock, but it's also created by an inverter (U1). You can try and characterise a 74x241. One of its enable pins is positive, the other negative. You might be lucky if their propagations are the same, but a quick first glance at the 74LS and 74HCT data sheets is discouraging. Still, this should be a simple test.

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Re: High resolution mode?

Post by PurpleGirl » 09 Oct 2019, 15:24

Would capacitors help smooth over the transition? And would the final chip need to be faster or slower? There are faster TTL-compatible chips, but if the signal before that is not changing fast enough, might that make it worse?

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Re: High resolution mode?

Post by alastair » 10 Oct 2019, 14:48

The fundamental issue here is the additional state. You only want two states: "Pixel 1" (state A) or "Pixel 2" (state B), but there is also a third state: "Update Pixels" (state C). You can try and adjust the timing and hide state C in the A->B or B->A state transition. This doesn't work though since the rate at which the logic changes from 0->1 and1->0 is different. You might be able to align one of these transitions, but the other will show up. Also, this requires critical timing adjustment that will change as the chips warm up.

The only solution is to add an additional register after the A/B selector using the faster dot clock (12.5 MHz). This will sample the A and B states and eliminate state C from the output. It's a simple fix but does require an additional chip

PS. I building something very similar and have been working though all these issues on a breadboard for the last 6 months :x

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Re: High resolution mode?

Post by marcelk » 17 Dec 2019, 22:56

A little bird slipped this under my door today: a cute 16-pinner that might work as a proper resolution doubler.

The idea is to clock the RS flip flops at 12.5 MHz on /CP. Feed the 6 color bits into the multiplexers, get 3 colors bits out in two phases.

The remaining flip flop and 2-to-1 multiplexer can function as a frequency divider: just hardwire its inputs to H an L. It then outputs a 50% duty cycle clock at 6.25 MHz. That can drive the rest of the system, including its own select line S.

SN74LS298.png (72.2 KiB) Viewed 755 times

Warning: I had a fever today, so I may still be hallucinating...

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Re: High resolution mode?

Post by tocksin » 01 Feb 2020, 02:39

Cleaning up the output with a register is good digital design. I can't seem to find a version that is CMOS and in DIP package and is not obsoleted. I'll keep looking. TTL would probably be ok. Still worst case is two chips, but it's much more slick with one. I'd still like to try the 4063 analog multiplexer chip - it looks like the select logic might be balanced in timing.

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