Extending the Gigatron instruction set

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tocksin
Posts: 16
Joined: 22 Jun 2018, 14:12

Re: Extending the Gigatron instruction set

Post by tocksin » 21 Sep 2018, 14:01

My new logic only requires a single extra (4x)OR chip, and I'd rather not have to add another chip. But I think I've figured out a way to have the override to select D on the lower byte without more chips. The problem is that I need an inverter and I don't have one. But I can have effectively an inverter by swapping the X and D inputs to the MUXL chips. I have to switch all the diodes on EL so that it behaves the same which means 2 more diodes. Now EL=0 selects D instead of X.

Now that I have my inverter, I can just connect /OVERRIDE to the EL line by another diode. So EL will act normally unless /OV=0, then EL = 0 and so MUXL=D. So getting that [X++,D] operation only costs an extra 3 diodes.

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marcelk
Posts: 139
Joined: 13 May 2018, 08:26

Re: Extending the Gigatron instruction set

Post by marcelk » 21 Sep 2018, 17:27

Some notes:

1. There is an unused multiplexer in U12 that can be turned into a slow inverter (and not much else because the select lines are shared with the other multiplexer). You would put the input on pin 15, keep pin 10 to 13 tied to Vcc and then get an inverted output on pin 9. It's a bit slow because the signal goes through 3 levels of logic, but it could result in a smaller change if the propagation delay is acceptable (probably not if it must go into the MAU).

2. The clock's duty cycle can be inferred from the scope images posted. I wouldn't trust the exact number of nanoseconds to reproduce well from board to board because I think it depends on the analog characteristics of the 74HCT04, which is a digital component...

3. About /OE, it is not that critical by itself: after all, /OE controls the last stage inside the RAM package. The datasheet gives tOE = 35 ns as a propagation time for 70 ns RAM (and 30 ns for 55 ns RAM).

4. Personally, I've always kept the goal of compatibility with 74LS parts and 70 ns RAM. I always believed that the SRAM was the anachronism in the design. However, people have been digging into old BYTE magazines for us, and surprisingly, 2147 (4096x1bit) "high speed" or "arcade" SRAM was available for $3.15 in... 1981. Ebay lists such parts with date codes as early as 1978. The slowest grade mentioned in data sheets I can find is 70 ns, and the March 1980 Intel application note AP-74 talks about speeds of 55 ns as if it is old news. I'm completely surprised by all of this. It's part of an interesting quest to date the Gigatron.

HGMuller
Posts: 20
Joined: 14 May 2018, 05:46

Re: Extending the Gigatron instruction set

Post by HGMuller » 21 Sep 2018, 21:49

This is indeed surprising. I was hooked on 2114 static NMOS RAMs (1K x 4), and the acces time I remember was 450ns! Hence I was happy if I could run at 2MHz. So I tend to look upon RAMs as very slow devices, and if I had to design something geared for speed, I would probably put the RAM on the fastest data path possible (address directly from the output of a register, or perhaps two tri-statable registers like 74x374 in parallel, and output directly clocked into a register through a dedicated bus), and even then allow multiple CPU cycles for one memory access. (E.g. do a memory write by applying an address to the RAM in one instruction, and then fetch the data (or store some) in a later instruction. Of course this poses the problem of how to feed it instructions fast enough, as the EPROM is also not very fast.

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