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Posted: 12 Dec 2019, 12:10
This just surfaced: a very entertaining presentation by Drass on his TTL implementation of the 6502, 65C02 and 6510. It can run at 20 MHz, which is on par with the TK20 from the 1980s (link
, link [German]
). Very worthwhile to watch.
The project page is here: https://c74project.com
Posted: 13 Dec 2019, 21:30
Yes, that is neat, and I bet it could go even faster when implemented in FPGA (and one implemented that way will do about 50 Mhz). But I see one shortcoming that should be easy to address. It seems to lack the "Sally" compatibility, so it won't work with an Atari computer without adding 4 additional chips. Ataris used the ANTIC chip which is pretty much a coprocessor and DMA controller. So ANTIC needs competition-free access to memory. The homebrew Atari clones use SRAM, so ANTIC doesn't have to pause the "Sally" 6502 as much since the SRAM eliminates the need for refresh.
Posted: 14 Dec 2019, 16:31
I doubt Drass is reading this forum. But you can propose your enhancement in the design thread on the 6502 forum: http://forum.6502.org/viewtopic.php?f=4&t=3493
Posted: 14 Dec 2019, 21:04
Yeah, thanks, that would be a good idea. Adding the /halt line to the design would increase compatibility with vintage systems. The Ataris that used the 6502 mostly used the "Sally" variant with the halt pin, though some of the older Ataris didn't use it. So they got MOS to add the halt line to simplify their boards. When ANTIC needs DMA access, it sends a signal to the /HALT line to pause the 6502 (similar to what is done in x86). So if you put a Sally chip in a regular 6502 socket, the circuitry and code would notice no difference, since the CPU would act like any other 6502 and the halt signal would be missing from the board. So the Sally mod is reverse compatible. But the boards designed around the Sally variant will only work with a Sally.
What would be neat would be to put one of these 6502 designs on an FPGA and put that on a 40-pin DIP adaptor board. That would offer increased performance due to both the clock rate and the expanded instruction set (I think I read that this one has 65816 compatibility with an expanded instruction set and 24 address lines) while being able to run the regular 6502 set.
Speaking of the C74-6502 project, they mentioned that they don't plan on making a version designed to work with different clock rates, I mean as an enhancement to vintage machines. I can understand that. That would likely require things like shift registers and cache (and maybe a halt line since the motherboard won't take data faster than it's clock).
Now if someone transferred this to FPGA (with the Sally mod) and put it on a 40-pin DIP board, someone would be free to modify their motherboard. That might require separating clock signals on the board, like maybe use a faster clock for the CPU but keep the original for other components. Or to make things even easier, it might be good to add a clock to the adaptor board and a jumper to get the signal from either the adaptor or the motherboard to increase the CPU clock without increasing any other clock (so ANTIC, GTIA, and PIA work the same). Ataris clocked at 1.89 Mhz for a reason, and I think that is because the NTSC color burst frequency is around 3.78 Mhz. So the other parts besides the CPU likely should still get 1.89 Mhz.
Posted: 15 Dec 2019, 14:20
There's quite a few 6502 (and variants) soft cores available for FPGA. The cycle accurate version on Open Cores
quotes 10MHz on a Spartan 3E, which is pretty obsolete at this point. You can probably get to 20MHz with the current Spartan 6 or 7.
Posted: 15 Dec 2019, 17:48
Yeah, but the FPGA in the Eclaire goes about 50 Mhz. The Eclaire implements the majority of the Atari 800, etc., in FPGA. So the "Sally" 6502, Antic, GTIA, PIA, and 2 Pokeys are all on a single chip. The original Ataris only use 1 Pokey for ports, keyboard, and sound. However, arcade games and homebrew Ataris use more for stereo sound and/or more than sound 4 channels. There was a quad Pokey for vintage arcade games.
This TTL build of the 6502 can go at 20 Mhz, wired, and is also 65816 compatible. So if it is converted to FPGA, it will go even faster than even the Rapidus upgrade (which goes at 20 Mhz). Adding the "Sally" mod will make it better than the Rapidus add-on since the official 65816 does not have a halt line either. So the Rapidus contains other chips to provide that functionality and convert some of the other signals to work in a 6502 socket, though less than what is needed to make a non-Sally 6502 work with the Antic chip. So if you add a /halt line, convert to FPGA, and maybe add some way to switch clocks in software for full vintage compatibility, you'd have something better than the Rapidus for upgrading Ataris.
Since this build seems to add the 65816 features on top of the 6502 features, it can give a much faster experience as a 6502, and software that takes advantage of 65816 access modes and instructions.
There are 8 more address lines than the 6502 due to 65816 compatibility, and what the 65816 does to access them is multiplex them with the data lines. That complicates motherboard circuitry if you want to access up to 4 Mb of memory. But if you ignore the extra lines, then you can only directly access 64K just like the 6502. The Ultra 1M upgrade for Ataris accesses a megabyte of RAM using software paging. The U1M replaces the ROM, and apparently the ROM does the paging.
Posted: 20 Dec 2019, 07:22
No, but I think Dieter does. He has read some of my posts.
Posted: 01 Feb 2020, 18:46
Drass mentions Gigatron in his youtube video, he might be aware of this forum.