SharmanCPU: a pipelined Von Neumann TTL CPU

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SharmanCPU: a pipelined Von Neumann TTL CPU

Post by marcelk »

Yesterday James Sharman posted this YouTube video where he demonstrates his TTL computer producing prime numbers.

Duration: 6m57s

SharmanCPU.jpg (363.29 KiB) Viewed 20926 times

To those who missed it, James has been working on his design for over a year. The whole design and build process is documented in an impressive series of almost 70 episodes, and still growing.

As so many others, this project was also sparked by the Ben Eater series. To make his computer unique and interesting, James set out to replace the SAP-1 architecture with his own 3-stage pipeline system. This gives him a Von Neumann architecture capable of executing close to 1 instruction per cycle. That is truly excellent.

And oh, it has a fast diode matrix for decoding the ALU operations, which made me smile. You can see in the middle of the board that other control signals come from four EEPROMs. Normally that is slow, but here their delays can be kept away from the critical path exactly because it's all pipelined. So while being clocked by a 555 timer, there's nothing holding it back from going many-MHz with a crystal.

Congratulations James!
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