No zero page banking needed for this read only browser. You can use a classic extension, but you need all the patches on the 1909 pcb.
Zero page banking will only be needed to make the os resident, in an undefined future. It might even be possible to do without, at the expense of saving and restoring about fifty bytes for each call.
Plus, GALs are period correct. They were introduced in 1985 and are functionally equivalent — but electrically erasable — to the 22V10 PALs of 1978, I believe.
Gigatron OS - Some progress and a (solved) hardware mystery.
Forum rules
Be nice. No drama.
Be nice. No drama.
Re: Gigatron OS - Some progress and a (solved) hardware mystery.
I was using Lattice GAL's in the early 90's and hadn't heard of them until around 1990, I also remember just how super power hungry they were back in the day, around 80-100mA for a 22v10 at 35ns from memory.
Re: Gigatron OS - Some progress and a (solved) hardware mystery.
It is true that PALs were common these times, but the Gigatron was designed as a TTL-only system. It even has diode matrix decoders. If Marcel and Walter had used GALs from the beginning, ALU and control logic would be significantly smaller. The whole system would fit onto an eurocard. But that was not the idea.
Re: Gigatron OS - Some progress and a (solved) hardware mystery.
These GALs are not CPLDs, and by a big margin. They certainly cannot contain the ALU. Two of them could have replaced the forest of diodes using almost a much pcb space as the diodes. No way to make an eurocard sized Gigatron with those! These GALs are just a reimplementation of the 22V10 chips of the late 70s, just like the 74HCT chips are reimplementation of the 74 series chips.
My personal interest for the Gigatron is not that it is period correct --no 55ns 32KBx8 SRAM in the 80s-- but what it teaches me. The Gigatron really shows how a computer work down to the level of gates. So I am all for keeping the forest of diodes because it taught me something. At the same time I find interesting to make expansion boards that use slightly more complicated parts just to understand how things have evolved. If you learn the Gigatron, then look at the GAL-based expansion, you can start wondering whether you could use such chips to replace the diode forest in a reprogrammable way. This is instructive. You can also observe that the GAL allows you to do an eight-way OR in about 10ns for the zero page banking address decoding whereas doing the same with cascaded 74xx chips would easily need 40ns. Why is it so? Does it explain some of the subsequent developments?
Anyway, we all have our reasons
![Smile :-)](./images/smilies/icon_e_smile.gif)