Almost any enhancement that could be made to the Gigatron would add chips. From my perspective I'm ok with that provided it is done sparingly with substantial benefit to be gained from those additions. I have my own philosophical view that I'd like to keep it to something that was theoretically buildable around 1979.
The standard Gigatron can put 4 things onto the bus. D, RAM, AC and IN Of those only RAM access and Immediate values use the second byte of the instruction. Nabbing the bottom two bits of D and the existing !IE and directing them into pins 13,14,15 of U11b gives a potential for three additional sources to put on the bus. (note U11b is currently being used as a 3 input OR It'll need some of a chip to replace that functionality)
IN0 retains the existing input IN1, IN2, IN3 are available for operations
The thing that stands out as worth adding in this way is a 74xx374 taking in the Output from the ALU bits 1..7 into 0..6 and Carry into bit 7. Placing the carry into a separate register at bit 0 would be more convenient for code but I think combining them into the one register gets you most of the advantages
This means Shift Right is much easier to do.
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LD [$24],AC LD IN1,AC AND $7f,AC // AC now has [$24]>>1 Strictly speaking the AND isn't necessary for a LD there's no carry anyway
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LD [A_Low],AC ADD [B_Low],AC ST [Result_Low] LD IN1,AC blt .carry LD [A_High],ac ADD [B_High],AC bra .done .carry: add 1,AC ADD [B_High],AC .done: ST [Result_High]
Utilizing the other two inputs would require at least a chip each to feed the bus and then whatever hardware needed to give them values. An easy option would be to to use a couple of 74xx244 chips fed from X and Y. That would make it fully possible to read X and Y which makes it feel a little more like a 6502, but I'm not sure if the benefits would be that great, using Zero page for workspace seems to be working well enough.
Another idea is potentially Latching PC before Jumps, The entire thing or just the Top byte. This could act as a link register which might provide the possibility to do some new things. I'd have to think about it some more, to be worth ding it would have to be significantly better than manually storing the return address in Zero Page.
One input could just be as simple as AC with the nybbles swapped. (surprisingly useful)
The first part is easy
[Y,X++],OUT becomes [Y,X++],PIXOUT
[D],OUT goes to the same place as before HSYNC and VSYNC still come from here
[Y,X++],PIXOUT goes to a 74xx273
A couple of gates using the existing !OL IX and !IX should give individual lines.
The PIXOUT 74xx273 goes into a 74xx157 toggled by a clock running at twice the CPU rate (so a clock divider also needed)
This should give a 16 colour highres output. Using my oddball resister net There's scope for a shift register here too. if the 157 were toggled by a shift register you could do bitmaps in any two of the 16 colours. (or just mono if you eliminate the 273)
I'm still in the speculation stage, but I'm working on putting this into the SimulIDE emulator. It might have to wait for v1.0 stable There are some bugs in the 74series chips on the 0.4.15 version.
Anyway it's 5-10 new chips for varying degrees of new features.