For an unconditional branch, the instruction bits are 111.
I maintain an experimental rom to play with all kind of crazy idea. I am particularly fond of the latest one which has to do with dispatching work using a low overhead finite state machine. Anyway, the compilation gives ominous warning because I am using a conditional branch to an address fetched from RAM
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1403 f52b bge [$2b]
Warning: large propagation delay (conditional branch with RAM on bus)
The offending code looks like this:
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FSM14_NEXT: 1401 8115 adda [$15] 6095 adda([vTicks]) #0 NEXT
1402 f52b bge [$2b] 6096 bge([fsmState]) #1
1403 c215 st [$15] 6097 st([vTicks]) #2
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# Warning for conditional branches with a target address from RAM. The (unverified) danger is
# that the ALU is calculating `-A' (for the condition decoder) as L+R+1, with L=0 and R=~A. But B
# is also an input to R and comes from memory. The addressing mode is [D], which requires high
# EH and EL, and this is slower when the diodes are forward biased from the previous instruction.
# Therefore R might momentarily glitch while B changes value and the AND/OR layers in the 74153
# multiplexer resettles. Such a glitch then potentially ripples all the way through two 74283
# adders and the control unit's 74153. This all depends on the previous instruction's addressing
# mode and the values of AC and [D], which we can't know with static analysis.
# See also https://github.com/kervinck/gigatron-rom/issues/78
First question: has anyone has actually observed this? Should this instruction branch unexpectedly, then the attached ROM cannot work. Yet, as far as I know, it works very well. Maybe Walter knows something about Marcel's original concern?
Second question: it seems that applying the same reasoning as Marcel's to U12 (the condition code decoder, also a multiplexer) suggests that if BRA[$dd] works, then so does BGE[$dd]. Can you see a flaw in the following argument?
The two selector bits of the condition code decoder are the very stable AC7 (the high bit of the accumulator flip-flop) and the potentially glitching C0 (the carry from the ALU). Together these two signals define the three possible conditions for the accumulator.
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{AC7,C0} AC is BRA BGE
---------------------------------
00 >0 y y
01 =0 y y
10 <0 y n
11 Illegal n n
The first three multiplexer inputs are tied to the instruction bits that determine when a branch should occur. For instance 100 means BGT, 110 means BNE, 111 means BRA, etc. The fourth multiplexer input is wired to the ground, which means that a glitching C0 could prevent a branch from happening even when the jump instruction is an unconditional branch. In fact we can compare BRA and BGE in two scenarios:
- When AC7 is 0, both are supposed to branch. A C0 glitch only affects the first two multiplexer AND gates because the last two are held low by /AC7. The situation of BRA and BGE is therefore exactly identical. If a glitch on C0 can cause BGE to fail, then it can also cause BRA to fail.
- When AC7 is 1, only BRA is supposed to branch. This time, the first two AND gates are safely held low by AC7 and are out of the picture. In the case of BGE, the last two gates are also safely held low by the multiplexer inputs, therefore we are certain that BGE does not branch. In the case of BRA, a glitch on C0 could temporarily cause the illegal combination 11 and prevent BRA from branching.