Design Choices of the Gigatron (and similar designs)

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Joined: 30 Sep 2020, 22:19

Design Choices of the Gigatron (and similar designs)

Post by Sugarplum »

I looked at the schematics and have some questions.

* Could the upper multiplexers driving the memory be replaced by a buffer? I notice that the multiplexers are not wired as I'd expect. The 2nd set of inputs are all tied high. I'd think they'd be tied low to mute the Y register and allow Page 0 instructions to work. But instead, Marcel has the selector line wired low and the line from the CU is driving the enable line, not the selector line. So that is being used as a tristate buffer and not as a multiplexer as intended. Is there an advantage to doing it this way when a multiplexer seems to be the right part? Does tri-stating the multiplexer even set the upper address lines sufficiently low? I mean, it must, obviously, as it works. Would there be a disadvantage to subbing a non-inverting tri-state

* If one wanted to replace the multiplexers and adders with a prepackaged ALU (such as the L4C383 or IDT7383) in a new design, it wouldn't have operations to change the PC or load/store. Obviously, the diode ROMs would need to be reconfigured to use such a chip for the things it can do. So, if the Gigatron were designed to not use the ALU for load and store, how would one do it? I guess one would alter a diode ROM for that to set the desired lines. Would changing that alter other behaviors such as causing the accumulator to not be clobbered when expected?

* Are there ways to redesign the CU to be faster? Would PALs be faster than the diode ROMs? Or, are there fast enough transistors to replace the diodes and resistors (and make things more like how a mask ROM works)? Or would there be a way to throw more circuitry at it? (For instance, the current ALU could be faster with just 2 more chips.) I'd have to keep studying the schematics. It took me a long time to understand the diode ROMs, but now I do. And I do wonder if adding non-inverting decoders for things that directly use the decoders and then invert the outputs be faster, slower, or break even. It's possible that non-inverting decoders are slower (since NOTted logic is supposedly faster due to the transistors used), but you wouldn't need inverters, so that might just break even. I guess I'd need to study the data sheets for that.
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