Producing ASIC's isn't that cheap (regular ones start at about 500 thousand). It also can only be ordered as die in amounts of 1000's, which of you would have to put an epoxy blob and pins? on. You could use some cheap FPGA chip that would be powerful enoough, Neverthless Gigatron-On-A-Chip (GoC suggestion anyone?) like the Nintendo-On-A-Chip (NoC) would be a success. I'm hope it works out well
Actually, ASIC costs are coming down. They now can do smaller orders by putting different products on the same wafer.
I, myself have considered coming up with an advanced Gigatron (on FPGA) with hardware video and a framebuffer, maybe a hardware PSG, maybe a programmable light sequencer that can be autonomous (so if you want to bit-bang it you can, but it can fake it when you need more power) if anyone would be interested, and perhaps a vCPU coprocessor. It would be neat if I did that if that could be turned into a SOC ASIC.
The NRE goes up exponentially with smaller nodes, but the older nodes are still reasonably cost effective. Regretfully, I never did get very far with this. While I do have a working prototype on FPGA, and got the OpenLANE toolchain installed, things suddenly got a lot busier at work starting August. Apparently companies are realizing in the midst of pandemic WFH that your address doesn't matter as much as the hours you keep and I've had 3 coworkers quit to "move" to CA, leaving me a little overwhelmed. I am still hopeful to get some time over Thanksgiving to devote to this. I just need to figure out how to instantiate the OpenRAM generated dual-port SRAM and the hooks to the RISC-V "test-harness", but I'm not hopeful on making the first shuttle.
Minor update on this. I missed the 11/30 shuttle. I was dependent on OpenRAM to generate the 64kx16 "ROM" and 64kx8 RAM for the design, but unfortunately they are still ironing out bugs and OpenRAM was not working at the time that the shuttle was launched. I tried to implement it in DFFs and the design did not look like it would fit the user space. One thing that I was wondering about is how small we could get the ROM image, perhaps remove all other programs such that it only contained Tiny BASIC and the Loader application, the goal being to reduce the ROM requirement and load everything via the Loader. Before I start looking at the gigatron-rom GitHub, is there a good tutorial for how to build the ROM from scratch? TIA!
It's non trivial to build a new ROM without the applications because you have to modify a number of *.gcl files that are hard coded to the applications themselves present within the ROM, as well as wrapping your head around how the build system works. But it's not all that difficult once you figure it out.
I have built a 'bmwtcu' ROM that contains only TinyBASIC and the Loader applications for you and attached it here:
@at67 OUTSTANDING WORK on the SDCard Browser!!! You're going to have to teach me how to build the minimal ROM!
PS - This video motivated me to build up my Pluggy Reloaded and I also finally got around to trying the bmwtcu image you created. When I use sendFile.py, the Gigatron resets and navigates down to TinyBASIC and enters it instead of loading the target gt1 file. I assume this is the result of hard-coded button presses assuming the full menu, and one way of working around it would be to remove TinyBASIC and only have the Loader option, or swap the Loader and TinyBASIC menu entry locations. I think that the problem would also go away with a custom SDCard Browser only ROM. Yes?