Re: Video Repeater
Posted: 23 Oct 2021, 19:21
Seems we need to invent a CTRL instruction scheme that provides for a substantial number of GPIOs. I believe that the scheme should not demand a different ROM for the ordinary operation of the ram and i/o expansion. It would be very inconvenient to have to use different ROMs for different expansion boards.
In the original design, bits 2 to 5 are four SPI select bits. In the GAL design, bits 2 and 3 are two SPI select bits, bit 4 indicates the SPI clock polarity, and bit 5 controls the zero page banking feature. Although bits 4 and 5 have a different meaning, setting them to 1 is the safe and compatible choice. Note that it is possible, to some extent, to change how the gal-based board operates by simply programming the GALs differently.
Since these additional GPIOs can be used as additional SPI select lines, I believe our best shot is to hijack bits 2 to 5. We should however make sure that the program that use a SD card on SPI0 (e.g. CardBoot) can control /SS0 by using bit 2. Note that Bit 3 and 4 are always 1 when they do so. I would also avoid touching bit 5 because the gal-based board stores in GAL1 while all other three bits 2, 3, 4, are managed by GAL2. And finally we would like to cleanly reset the board state (including the GPIOs) when bits 2 to 4 are all set to 1 because this is how the Gigatron initializes the board on reset.
Here is attempt.
Update: This is way too complicated
In the original design, bits 2 to 5 are four SPI select bits. In the GAL design, bits 2 and 3 are two SPI select bits, bit 4 indicates the SPI clock polarity, and bit 5 controls the zero page banking feature. Although bits 4 and 5 have a different meaning, setting them to 1 is the safe and compatible choice. Note that it is possible, to some extent, to change how the gal-based board operates by simply programming the GALs differently.
Since these additional GPIOs can be used as additional SPI select lines, I believe our best shot is to hijack bits 2 to 5. We should however make sure that the program that use a SD card on SPI0 (e.g. CardBoot) can control /SS0 by using bit 2. Note that Bit 3 and 4 are always 1 when they do so. I would also avoid touching bit 5 because the gal-based board stores in GAL1 while all other three bits 2, 3, 4, are managed by GAL2. And finally we would like to cleanly reset the board state (including the GPIOs) when bits 2 to 4 are all set to 1 because this is how the Gigatron initializes the board on reset.
Here is attempt.
Code: Select all
Bits 4 3 2
1 1 1 --> /ss0 deactivated. All GPIOS reset to default state1
0 1 1 --> /ss0 deactivated. GPIOs are not changed
1 1 0 --> /ss0 activated. putting back bit 2 to 1 will reset all the GPIOs.
0 1 0 --> /ss0 activated. putting back bit 2 to 1 will not change the GPIOs
p 0 1 --> not sure. /SS1 on the gal based board?
p 0 0 --> control word that the GPIOs
- p is the SPI clock polarity (in case we need to implement different SPI modes)
- High byte controls the GPIOs. For instance ggggpppp where pppp
is a page number and gggg sets four GPIOs in page pppp.