Gigatron 512k and more

Using, learning, programming and modding the Gigatron and anything related.
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lb3361
Posts: 186
Joined: 17 Feb 2021, 23:07

Gigatron 512k and more

Post by lb3361 »

Because we can.

There is more to it than just 512k....


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lb3361
Posts: 186
Joined: 17 Feb 2021, 23:07

Re: Gigatron 512k and more

Post by lb3361 »



This project is in fact a platform for experimenting with lots of crazy ideas. This is a collaboration with Hans61 who convinced me to go ahead and did a lot of debugging. The expansion board plugs into both the SRAM socket and the output register, an idea inspired by Axelb's amazing video repeater. This was a game changer because the output register has a clock signal that was sorely missing in my earlier expansion boards.

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The SMT chips are hidden below. This is definitely not for purists, but it allows for experimenting with a lot of strange ideas.

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More to come...
Last edited by lb3361 on 16 Jan 2022, 22:59, edited 1 time in total.
Hans61
Posts: 62
Joined: 29 Dec 2020, 16:15
Location: Saxonia
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Re: Gigatron 512k and more

Post by Hans61 »

Thanks to lb3361 for the great work. A big step for the Gigatron.
lb3361
Posts: 186
Joined: 17 Feb 2021, 23:07

Re: Gigatron 512k and more

Post by lb3361 »

Technical info

The core of the board is a XC95144XL CPLD with a 100 pins package mediating access to a 512KB static RAM that is fast enough to perform multiple reads or writes during a single Gigatron cycle. For instance, in a single cycle, one could serve the Gigatron memory requests and fetch pixels from the memory to drive the VGA output. Of course, and this is the point of this board, we can easily change what the board does by reprogramming the CPLD. There is also a PLL chip that produces clocks at 2x and 4x the frequency of the 6.25Mhz Gigatron clock, a 74LVC244 that saves I/O pins by commuting the low address bits, and a LDO to produce the required 3.3v.

The various directories of https://github.com/lb3361/gigatron-lb/t ... sion-crazy have many README files that go over many of the details. Note that all this is highly experimental and will most likely stay that way.

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At this point we had success with:
  • Extended banking to access the 512Kb of memory.
  • Video snooping to run the vCPU at full speed while displaying pixels, using a patched ROM.
  • Relocating the video buffer in a high memory bank to free all 64Kb of directly accessible memory.
  • Doubling the horizontal resolution (320x120 pixels, 52x15 characters).
  • Also doubling the vertical resolution (320x240 pixels, 52x30 characters), using a patched ROM.
  • Forwarding 6 bits audio to an extension pin using pulse modulation.
  • Running Marcel's Simple Chess Program, MSCP, https://www.chessprogramming.org/MSCP, on a real Gigatron, albeit a bit puffed up.
Pics later...
Last edited by lb3361 on 16 Jan 2022, 22:58, edited 1 time in total.
lb3361
Posts: 186
Joined: 17 Feb 2021, 23:07

Re: Gigatron 512k and more

Post by lb3361 »

Video snooping

Here is a video of a Gigatron 512K running at full speed regardless of the video mode:

https://www.youtube.com/watch?v=m51MAn-iThs

Note that the Gigatron cpu is still fully in charge of the timing. The only difference the board makes is the fact that the Gigatron cpu only needs to execute an output instruction for the first pixel of each scanline (i,e., an output instruction that reads from memory outside page zero). The board then autonomously fetches successive pixels until the Gigatron cpu stops the process by outputting something that is not a pixel (i.e., an output instruction that does not read memory or reads memory in page zero). With a regular ROM, this does not change anything. This video was taken with a patched ROM that runs vCPU instruction between the first and last pixels of each scanline.

Axelb's video repeater performs similarly but in a very different way. It works by selecting video mode 3 in which the Gigatron only sends one out of four scanlines. The repeater then records what the Gigatron sends during the first scanline and plays it again during the next three scanlines. This opens three out of four scanlines for the vCPU with a display that resembles mode 0 or mode 1 depending on a jumper position (I believe.)

The video also shows that the Gigatron 512K starts in mode 2 by default (showing only scanlines A and C). Switching the video mode with the Select button cycles between modes 0, 1, and 2. Mode 3 is gone for internal reasons...
bmwtcu
Posts: 111
Joined: 01 Nov 2018, 12:02

Re: Gigatron 512k and more

Post by bmwtcu »

Nice work! Fun fact, I had to do an exhaustive fit, but I got the entire Gigatron (less SRAM and ROM) to fit in the XC95144 part!
lb3361
Posts: 186
Joined: 17 Feb 2021, 23:07

Re: Gigatron 512k and more

Post by lb3361 »

bmwtcu wrote: 17 Jan 2022, 03:19 Nice work! Fun fact, I had to do an exhaustive fit, but I got the entire Gigatron (less SRAM and ROM) to fit in the XC95144 part!
This is a nice way to characterize the size of this part. I gave it a try : https://github.com/lb3361/gigatron-lb/t ... razy/bonus. However I could not make the Gigatron fit without moving the serial input register logic into an external 74HCT595. My design comes four macrocells short.
lb3361
Posts: 186
Joined: 17 Feb 2021, 23:07

Re: Gigatron 512k and more

Post by lb3361 »

Video banking

Because we do not rely on the Gigatron CPU to read the pixel values, we no longer have to place the video buffer in the current address space of the CPU. We can displace it into another bank that we only access when we want to write something to the screen. This frees almost all of the 64KB address space for programs and data (minus the audio buffers and the video table.)

In a brief comment in the Gigatron ROM Makefile https://github.com/kervinck/gigatron-ro ... efile#L299, Marcel spoke about a moon shot: getting his chess program, MSCP, to work on the Gigatron. He encountered a lot of problems with the C compiler crashing for obscure reasons. When I rewrote the C compiler, MSCP was high on my list of things to run. Alas MSCP in its default form requires about 56KB of memory to run. I was able to run it in the GLCC emulator, but not on a real Gigatron viewtopic.php?p=2379#p2379.

Displacing the video buffer outside of the 64KB address space changes this. The only thing I had to do was to write a customized version of the GLCC console library and compile MSCP. This is a very slow chess player. Anyway, I believe this is the first time MSCP runs on a real Gigatron, although I gladly recognize that this Gigatron is a bit puffed up.

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Last edited by lb3361 on 17 Jan 2022, 19:36, edited 6 times in total.
walter
Site Admin
Posts: 137
Joined: 13 May 2018, 08:00

Re: Gigatron 512k and more

Post by walter »

Although the board is certainly different from the Gigatron itself in terms of design, I must say it is very cool it is playing MSCP. Marcel would have loved that. Well done.
axelb
Posts: 26
Joined: 07 Jan 2021, 06:27

Re: Gigatron 512k and more

Post by axelb »

Great development! Even a resolution of about 256 x 240 would enable us to mimic some Arcade classics like Moon Patrol, Frogger etc…
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