Tapping the ROM
Posted: 12 Feb 2022, 07:04
While I may never try this, I just got a brainstorm from the 512K thread and Jeff Laughton's KimKlone.
https://laughtonelectronics.com/Arcana/ ... intro.html
A point raised in the 512K thread was that most ideas discussed over the years could be realized through the RAM and output register sockets. I pondered that other ideas could be realized by tapping the ROM and the accumulator. For instance, a coprocessor to add shifts, multiply, more registers, etc. could sit in the ROM and Ac sockets. That could be a way to add a discrete stack with its own SP and all. One could put new registers on such a board and easily copy to/from the Ac. As for interacting with the other registers, such a board could intercept and substitute the new instructions with immediate instructions. So moving from a 2nd accumulator or a W or Z register to X or Y could be a matter of the coprocessor board running the instructions in tandem with the Gigatron performing an immediate operation to X/Y.
That idea comes from Jeff Laughton's KimKlone which added an "exoskeleton" CPU wrapper that intercepted the undocumented opcodes of the 65c02. For some things, it just intercepted the opcodes and acted upon its own registers. They were already NOPs, so the CPU ignored those anyway. For other things, it would act on the opcodes and substitute what went to the 65c02 to work synergistically with it.
So one could do something similar with the Gigatron if they wanted to. So if you wanted to add extra registers, intercepting the ROM and the accumulator would be enough for most tasks, and if you want to move from new registers to X/Y, the board could change the opcodes to store immediates while using the original opcodes for itself. For other instructions, the board could perform the new instructions while forwarding a NOP to the Gigatron. It wouldn't even have to be the most elegant since it could send "dirty NOPs" with random "garbage" in the operand byte. And this board idea could even be used to apply my idea of a secondary ALU where unused immediate space could do things SIMD/"VLIW" style. And all of these changes would need a new ROM.
If a ROM board adds an upper index register, one could make a RAM board or a combined I/O and ROM coprocessor board and have a bus from a new native register to more RAM address lines. That might be more elegant than using command sequences to do similar.
https://laughtonelectronics.com/Arcana/ ... intro.html
A point raised in the 512K thread was that most ideas discussed over the years could be realized through the RAM and output register sockets. I pondered that other ideas could be realized by tapping the ROM and the accumulator. For instance, a coprocessor to add shifts, multiply, more registers, etc. could sit in the ROM and Ac sockets. That could be a way to add a discrete stack with its own SP and all. One could put new registers on such a board and easily copy to/from the Ac. As for interacting with the other registers, such a board could intercept and substitute the new instructions with immediate instructions. So moving from a 2nd accumulator or a W or Z register to X or Y could be a matter of the coprocessor board running the instructions in tandem with the Gigatron performing an immediate operation to X/Y.
That idea comes from Jeff Laughton's KimKlone which added an "exoskeleton" CPU wrapper that intercepted the undocumented opcodes of the 65c02. For some things, it just intercepted the opcodes and acted upon its own registers. They were already NOPs, so the CPU ignored those anyway. For other things, it would act on the opcodes and substitute what went to the 65c02 to work synergistically with it.
So one could do something similar with the Gigatron if they wanted to. So if you wanted to add extra registers, intercepting the ROM and the accumulator would be enough for most tasks, and if you want to move from new registers to X/Y, the board could change the opcodes to store immediates while using the original opcodes for itself. For other instructions, the board could perform the new instructions while forwarding a NOP to the Gigatron. It wouldn't even have to be the most elegant since it could send "dirty NOPs" with random "garbage" in the operand byte. And this board idea could even be used to apply my idea of a secondary ALU where unused immediate space could do things SIMD/"VLIW" style. And all of these changes would need a new ROM.
If a ROM board adds an upper index register, one could make a RAM board or a combined I/O and ROM coprocessor board and have a bus from a new native register to more RAM address lines. That might be more elegant than using command sequences to do similar.