Novatron

Using, learning, programming and modding the Gigatron and anything related.
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alastair
Posts: 65
Joined: 10 Oct 2019, 14:28

Novatron

Post by alastair »

I finally found some time to finish up the Novatron design discussed here.
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I decided to switch from Pluggy Reloaded to a slightly stripped down version of Marcel's expansion board (still untested). It has 2 SPI ports; with one connected to a board-mounted SD card and the other to a header. There are a couple of mounting holes either side of the RAM for an expansion card. This could connect to the SPI1 header, or if you wanted more options then the onboard expander can be bypassed by jumpers (as shown) and you can go directly to the RAM socket. This way one of the other expander designs could be plugged in (although you are starting from a 32-pin DIP rather than the Gigatron 28-pin).
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Note the original EDI 1M bit static RAM chip - date code 1994 but originally released in 1989 8-)

The board is wired for 6-bit audio, so there are only two blinken lights available and these are connected to a single bi-color LED. There is an additional 74F157 on board and switch to select between the standard 64-color "low-res" mode and an 8-color hi-res mode. One of the (possible) design goals of the board is to support CP/M as discussed in this post by Marcel. The board is using F-series chips and runs fine at 12.5Mz.

The main delta between the Gigatron and Novatron is the use of GALs to replace the diode ROMs and ALU multiplexers. The expansion also uses a GAL but this only implements a few gates from the original expansion card. I've attached the schematic, but warning! Everything is crammed in to just 3 pages, so it might be a bit hard to follow.
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novatron-schematic-v1.3.pdf
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I'll be demoing this at VCF Midwest next month with the plan to offer a kit in another month or two. I plan to include a Famicom controller but just realized you might need to yank out the ATtiny85 to make this work... still a few things to figure out here :D
bmwtcu
Posts: 132
Joined: 01 Nov 2018, 12:02

Re: Novatron

Post by bmwtcu »

Nice!!! You should be able to split the PULSE and LATCH pins and use a switch to select between keyboard and controller DATA? I've never tried swapping mid-stream, so not sure if you can get away without a reset for some edge conditions. While I understand the tradeoff you made for the RAM expander over the Pluggy Reloaded, I'm curious what your intent is from a ROM support standpoint? Are you shipping your kit with a custom DEVROM to enable the expander SD Browser?
lb3361
Posts: 235
Joined: 17 Feb 2021, 23:07

Re: Novatron

Post by lb3361 »

Very nice.

I wouldn't burn the SPI SD card browser in the Rom. As long as Cardboot is there, it is enough to put it on the SD card itself. Si the DEVROM should do...

Did you use level shifters for the sd card signals MOSI, SCLK, /SS0 ? I believe one has to...
alastair
Posts: 65
Joined: 10 Oct 2019, 14:28

Re: Novatron

Post by alastair »

bmwtcu wrote: 13 Aug 2022, 07:12 You should be able to split the PULSE and LATCH pins and use a switch to select between keyboard and controller DATA?
I'm not sure if the Famicom controller output is open collector/drain. If so they I could leave both connected. Plugging in the controller would probably prevent the keyboard from being reliable. I'll do some experiments when the controllers finally arrive from China.
lb3361 wrote: 13 Aug 2022, 13:56 Did you use level shifters for the sd card signals MOSI, SCLK, /SS0 ? I believe one has to...
No level shifters. I'm sticking with TTL chips and I'm hoping those logic levels work. The typical TTL high output is around 3.4v under nominal load, but it might get closer to 4v if the SD card pulls no input current. The SD card specs put a maximum of VDD+0.3 on the input voltage (3.6v), so I may need another resistor network connected to ground on MOSI/SCLK etc (the current networks I'm using pull the TTL high level below 3.2v). Anything over 2v is good as a high for TTL input.

I will probably ship a slightly modified ROM but keep it close to 5a. Cardboot might be a good option.
lb3361
Posts: 235
Joined: 17 Feb 2021, 23:07

Re: Novatron

Post by lb3361 »

Oh I see. No level shifters because the 74f series (and other ttl) have a lower Voh than the 74hct ones (and other cmos).
alastair
Posts: 65
Joined: 10 Oct 2019, 14:28

Re: Novatron

Post by alastair »

I spent yesterday trying to debug the expander. I think I just figured it out though. I was using the schematic from Marcel's original Hackaday.io project... but those assignments don't match what is used in the code here:

Code: Select all

# Setup I/O and RAM expander
ctrl(0b01111100)                # Disable SPI slaves, enable RAM, bank 1
#      ^^^^^^^^
#      |||||||`-- SCLK
#      ||||||`--- Not connected
#      |||||`---- /SS0
#      ||||`----- /SS1
#      |||`------ /SS2
#      ||`------- /SS3
#      |`-------- B0
#      `--------- B1
# bit15 --------- MOSI = 0
I haven't been following the expander development discussions and it looks like I missed something :cry: I'll need to catch up and see if I should change the code or change the board.

<edit1> I just found this...
lb3361 wrote: 25 Oct 2021, 03:08 In the last iteration of the original expansion board, these sixteen bits are used as follows:
  • A0 controls the SPI clock and whether the Gigatron reads from the RAM or from the MISO lines.
  • A1 is not connected and not usable because a smart optimization causes A1 to go up and down during SPI operations.
  • A2..5 control four SPI device selection lines
  • A6..7 control the RAM bank presented in the upper half of the address space (128KB = 32KB * 4)
  • A8..14 are not connected but are not usable because they go up and down during SPI operations.
  • A15 controls the SPI MOSI line.
I'm starting to see a Rev.4 board in my future :roll:

<edit2> Ok, I found the post where this changed. I guess I'm 3 years out of date and was not "playing along at home" :lol:
lb3361
Posts: 235
Joined: 17 Feb 2021, 23:07

Re: Novatron

Post by lb3361 »

There is also a bit of a problem about the MISO lines. Marcel used to pull them down and route them to bits 0 to 3 of the bits when sclk is high. The rom code assumes that the only non zero MISO must the one from the active spi device, and therefore can be tested with a simple anda(0xf). Alas many devices do not work like this...

The most robust approach is to mux the various MISOx lines into bit0 according to the state of the /SSx lines.
alastair
Posts: 65
Joined: 10 Oct 2019, 14:28

Re: Novatron

Post by alastair »

Thanks @lb3351 I'll try making that change. I've been following the instructions for you dev ROM here, but no luck yet (I'm using the files from the `binaries` folder).
lb3361
Posts: 235
Joined: 17 Feb 2021, 23:07

Re: Novatron

Post by lb3361 »

1) As long as your only using one spi device, Marcel’s approach works. The miso mux is only needed if you want to put two (or more) spi devices.

2) To use the spi browser, you need the devrom. Then you need to check that the gigatron boot enters CardBoot instead of the main menu when a SD card is inserted. If you tell me what you see on the screen, I can suggest debugging actions. Also CardBoot has plenty of commented out debugging output that can be turned on..

3) You also need to make sure the banking works. You should also test spi outputs with a voltmeter first because the SD card only makes it much more complicated.
alastair
Posts: 65
Joined: 10 Oct 2019, 14:28

Re: Novatron

Post by alastair »

I see the standard start screen with/without the SD card inserted. I can swap the SPI interfaces to use the header as SPI0 and test with an SD card breakout in case that's the issue. I can also turn on more debug in CardBoot.

I've run other versions of the ROM and seen it report 128k RAM. I'm not sure how robust that test is and I'm not sure if there's a specific program to do a better RAM test.
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