I looked again at the novatron schematics (from this thread) and I see that bus0/bus1 are connected to outputs of the U31 gal.
I assume that these outputs are only driven when sclk=1 and /oe=0 with. At the same time /woe should be 1 to prevent the ram from driving the bus. Does this mean that bus2 and bus3 are floating when this happens. This is important because the SPI code in the rom does not sort out what's on each bus line. It simply asserts sclk, reads a byte, ands with 0xf, and checks whether the result is zero or not. Therefore, one reads a 1 if any of the bus0123 is high, without regards to which spi port is active. So if bus123 are floating, one can easily read incorrectly from the spi device.
This works with Marcel's expansion because it pulls down all the miso0123 lines. This is a bad idea because many spi devices want a pull up instead. My solution was to make sure that when sclk=0, the bus lines bus321 are always zero, and bus0 reflects the miso of the active device. To do this one needs to have the /ss0 /ss1 signals (which U35 does not have. Note that I am using 22v10s, not 16v8s in the expansion).
The SPI code looks like this:
Code: Select all
for i in range(8):
st([vTmp],Y);C('Bit %d'%(7-i))#23+i*12
ld([sysArgs+4],X) #24+i*12
ctrl(Y,Xpp) #25+i*12 Set MOSI
ctrl(Y,Xpp) #26+i*12 Raise SCLK, disable RAM!
ld([0]) #27+i*12 Get MISO
anda(0b00001111) #28+i*12 This is why R1 as pull-DOWN is simpler
beq(pc()+3) #29+i*12
bra(pc()+2) #30+i*12
ld(1) #31+i*12
ctrl(Y,X) #32+i*12,29+i*12 (Must be idempotent) Lower SCLK
adda([vTmp]) #33+i*12 Shift
adda([vTmp])
If indeed MISO0 drives BUS0, then one could test the theory by replacing anda(0xf) by anda(0x1). Since this is an easy patch, I just did that in the attached rom (leaving all the debug output as well, meaning that the load is a bit slow. But it would be interesting to see if this works better. Of course this patch means that only SPI0 works, but this is a good way to know....
